9DMV0431 Data Sheet PDF | IDT





(Datasheet) 9DMV0431 PDF Download

Part Number 9DMV0431
Description 2:4 1.8V PCIe Gen1-2-3 Clock Mux
Manufacture IDT
Total Page 12 Pages
PDF Download Download 9DMV0431 Datasheet PDF

Features: 2:4 1.8V PCIe Gen1-2-3 Clock Mux 9DMV04 31 DATASHEET General Description The 9DMV0431 is a member of IDT's SOC-Frien dly 1.8V Very-Low-Power (VLP) PCIe Gen1 -2-3 family. Each of the 4 outputs has its own dedicated OE# pin for optimal s ystem control and power management. The part provides asynchronous and glitch- free switching modes. Recommended Appli cation 2:4 PCIe Gen1-2-3 clock multiple xer Output Features • 4 -Low-Power (L P) HCSL DIF pairs Key Specifications DIF additive cycle-to-cycle jitter <5 ps • DIF phase jitter is PCIe Gen1-2- 3 compliant • Additive phase jitter @ 125MHz: 420fs rms typical (12kHz to 20 MHz) • DIF output-to-output skew <50p s Features/Benefits • LP-HCSL output s; save 8 resistors compared to standar d HCSL outputs • 1.8V operation; 36mW typical power consumption • Selectab le asynchronous or glitch-free switchin g; allows the mux to be selected at pow er up even if both inputs are not runni ng, then transition to glitch-free switching mode • Spread Sp.

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9DMV0431 datasheet
2:4 1.8V PCIe Gen1-2-3 Clock Mux
9DMV0431
DATASHEET
General Description
The 9DMV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe Gen1-2-3 family. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 -Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 420fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
1.8V operation; 36mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 200MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMV0431 REVISION B 01/26/15
1
©2015 Integrated Device Technology, Inc.

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