MOSFET. FDMD85100 Datasheet

FDMD85100 Datasheet PDF, Equivalent


Part Number

FDMD85100

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 11 Pages
PDF Download
Download FDMD85100 Datasheet PDF


FDMD85100 Datasheet
September 2015
FDMD85100
Dual N-Channel PowerTrench® MOSFET
Q1: 100 V, 48A, 9.9 mΩ Q2: 100 V, 48A, 9.9 mΩ
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A
„ Max rDS(on) = 16.4 mΩ at VGS = 6 V, ID = 8 A
Q2: N-Channel
„ Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A
„ Max rDS(on) = 16.4 mΩ at VGS = 6 V, ID = 8 A
„ Ideal for flexible layout in primary side of bridge topology
„ Termination is Lead-free and RoHS Compliant
„ 100% UIL tested
„ Kelvin High Side MOSFET drive pin-out capability
This device includes two 100V N-Channel MOSFETs in a dual
Power (5 mm X 6 mm) package. HS source and LS Drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Applications
„ Synchronous Buck : Primary Switch of Half / Full Bridge
Bonverter for Telecom
„ Motor Bridge : Primary Switch of Half / Full Bridge Converter
for BLDC Motor
„ MV POL : 48V Synchronous Buck Switch
„ Half/Full Bridge Secondary Synchronous Rectification
Top Bottom
Pin 1
D2/S1
D2/S1
D2/S1
S2 G2
G1
GR
G2
D2/S1
D1 D1
D1
GR
G1
Pin 1
Power 5 x 6
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
VGS
ID
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
Drain Current -Continuous
-Pulsed
Parameter
TC = 25 °C
TC = 100 °C
TA = 25 °C
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
D1
D1
(Note 5)
(Note 5)
(Note 4)
(Note 3)
D2/S1
D2/S1
Q1 Q2
100 100
±20 ±20
48 48
30
10.41a
30
10.41b
261 261
294 294
50
2.21a
50
2.21b
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Package Marking and Ordering Information
2.5
551a
2.5
55 1b
°C/W
Device Marking
FDMD85100
Device
FDMD85100
Package
Power 5 x 6
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDMD85100 Rev.1.2
1
www.fairchildsemi.com

FDMD85100 Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
ID = 250 μA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
VDS = 80 V, VGS = 0 V
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
Type Min. Typ. Max. Units
Q1 100
Q2 100
V
Q1
Q2
72
70
mV/°C
Q1
Q2
1
1
μA
Q1
Q2
±100
±100
nA
On Characteristics
VGS(th) Gate to Source Threshold Voltage
ΔVGS(th) Gate to Source Threshold Voltage
ΔTJ Temperature Coefficient
rDS(on) Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 10.4 A
VGS = 6 V, ID = 8 A
VGS = 10 V, ID = 10.4 A, TJ = 125 °C
VGS = 10 V, ID = 10.4 A
VGS = 6 V, ID = 8 A
VGS = 10 V, ID = 10.4 A, TJ = 125 °C
VDD = 5 V, ID = 10.4 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
2.0 3.1 4.0
2.0 3.0 4.0
V
-11
-10
mV/°C
7.8 9.9
12.6 16.4
14.7 18.7 mΩ
7.8 9.9
12.9 16.4
14.6 18.6
27
26
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VDS = 50 V, VGS = 0 V
f = 1 MHz
Q1
Q2
1590 2230
1485 2080
pF
Q1
Q2
334 470
337 475
pF
Q1
Q2
13
13
23
23
pF
Q1 0.1 1.5 3.8
Q2 0.1 1.3 3.3
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg(TOT) Total Gate Charge
Qg(TOT) Total Gate Charge
Qgs Gate to Source Charge
Qgd Gate to Drain “Miller” Charge
VDD = 50 V, ID = 10.4 A
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 6 V
VDD = 50 V, ID
=10.4 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
14 25
12.5 23
5 10
5.6 11
19 30
18 32
4.2 10
4.4 10
22 31
21 29
14 20
13.5 19
7.3
6.8
4.3
4.4
ns
ns
ns
ns
nC
nC
nC
nC
©2015 Fairchild Semiconductor Corporation
FDMD85100 Rev.1.2
2
www.fairchildsemi.com


Features Datasheet pdf FDMD85100 Dual N-Channel PowerTrench® M OSFET September 2015 FDMD85100 Dual N-Channel PowerTrench® MOSFET Q1: 100 V, 48A, 9.9 mΩ Q2: 100 V, 48A, 9.9 mΩ Features General Description Q1: N- Channel „ Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A „ Max rDS(on) = 1 6.4 mΩ at VGS = 6 V, ID = 8 A Q2: N-Ch annel „ Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A „ Max rDS(on) = 16. 4 mΩ at VGS = 6 V, ID = 8 A „ Ideal f or flexible layout in primary side of b ridge topology „ Termination is Lead-f ree and RoHS Compliant „ 100% UIL test ed „ Kelvin High Side MOSFET drive pin -out capability This device includes t wo 100V N-Channel MOSFETs in a dual Pow er (5 mm X 6 mm) package. HS source and LS Drain internally connected for half /full bridge, low source inductance pac kage, low rDS(on)/Qg FOM silicon. Appli cations „ Synchronous Buck : Primary S witch of Half / Full Bridge Bonverter f or Telecom „ Motor Bridge : Primary Sw itch of Half / Full Bridge Converter for BLDC Motor „ MV POL :.
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