MOSFET. FDMD82100L Datasheet

FDMD82100L Datasheet PDF, Equivalent


Part Number

FDMD82100L

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 8 Pages
PDF Download
Download FDMD82100L Datasheet PDF


FDMD82100L Datasheet
June 2014
FDMD82100L
Dual N-Channel PowerTrench® MOSFET
100 V, 24 A, 19.5 mΩ
Features
General Description
„ Max rDS(on) = 19.5 mΩ at VGS = 10 V, ID = 7 A
„ Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 5.7 A
„ Ideal for flexible layout in primary side of bridge topology
„ Termination is Lead-free and RoHS Compliant
„ 100% UIL tested
„ Kelvin High Side MOSFET drive pin-out capability
This device includes two 100V N-Channel MOSFETs in a dual
Power (3.3 mm X 5 mm) package. HS source and LS Drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Applications
„ Synchronous Buck : Primary Switch of Half / Full bridge
converter for telecom
„ Motor Bridge : Primary Switch of Half / Full bridge converter
for BLDC motor
„ MV POL : 48V Synchronous Buck Switch
Pin 1
Power 3.3 x 5
D1 1
D1 2
D1 3
G2 4
S2 5
S2 6
12 G1
11 G1R
10 D2/S1
9 D2/S1
8 D2/S1
7 D2/S1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-Pulsed
Single Pulse Avalanche Energy
TC = 25 °C
TA = 25 °C
TA = 25 °C
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
(Note 1b)
Ratings
100
±20
24
7
80
150
38
2.1
1
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
3.3
60
130
°C/W
Device Marking
82100L
Device
FDMD82100L
Package
Power 3.3 x 5
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
1
www.fairchildsemi.com

FDMD82100L Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
100
V
ID = 250 μA, referenced to 25 °C
70 mV/°C
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
±100
μA
nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
1.0 1.7 3.0
V
ID = 250 μA, referenced to 25 °C
-6 mV/°C
VGS = 10 V, ID = 7 A
VGS = 4.5 V, ID = 5.7 A
VGS = 10 V, ID = 7 A, TJ = 125 °C
VDD = 5 V, ID = 7 A
13.5
17.9
25
29
19.5
30
36
mΩ
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 50 V, VGS = 0 V
f = 1 MHz
1130 1585 pF
173 245 pF
8.1 15 pF
0.1 1.8 3.6 Ω
Switching Characteristics
td(on)
tr
td(off)
tf
Qg(TOT)
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 50 V, ID = 7 A
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V VDD = 50 V
ID = 7 A
7.9 16 ns
2.8 10 ns
21 34 ns
2.9 10 ns
17 24 nC
8 12 nC
3 nC
2.3 nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 7 A
(Note 2)
0.8 1.2
V
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IF = 7 A, di/dt = 100 A/μs
42 67 ns
39 62 nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 130 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 150 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 10 A, VDD = 90 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 31 A.
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
2
www.fairchildsemi.com


Features Datasheet pdf FDMD82100L Dual N-Channel PowerTrench® MOSFET June 2014 FDMD82100L Dual N-C hannel PowerTrench® MOSFET 100 V, 24 A , 19.5 mΩ Features General Descripti on „ Max rDS(on) = 19.5 mΩ at VGS = 10 V, ID = 7 A „ Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 5.7 A „ Ideal for flexible layout in primary side of bri dge topology „ Termination is Lead-fre e and RoHS Compliant „ 100% UIL tested „ Kelvin High Side MOSFET drive pin-o ut capability This device includes two 100V N-Channel MOSFETs in a dual Power (3.3 mm X 5 mm) package. HS source and LS Drain internally connected for half /full bridge, low source inductance pac kage, low rDS(on)/Qg FOM silicon. Appli cations „ Synchronous Buck : Primary S witch of Half / Full bridge converter f or telecom „ Motor Bridge : Primary S witch of Half / Full bridge converter f or BLDC motor „ MV POL : 48V Synchron ous Buck Switch Pin 1 Power 3.3 x 5 D 1 1 D1 2 D1 3 G2 4 S2 5 S2 6 12 G1 11 G1R 10 D2/S1 9 D2/S1 8 D2/S1 7 D2/S1 MOSFET Maximum Ratings TA.
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