MOSFET. FDMS3615S Datasheet

FDMS3615S Datasheet PDF, Equivalent


Part Number

FDMS3615S

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 16 Pages
PDF Download
Download FDMS3615S Datasheet


FDMS3615S Datasheet
FDMS3615S
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
August 2011
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 5.8 mΩ at VGS = 10 V, ID = 16 A
„ Max rDS(on) = 8.3 mΩ at VGS = 4.5 V, ID = 13 A
Q2: N-Channel
„ Max rDS(on) = 3.4 mΩ at VGS = 10 V, ID = 18 A
„ Max rDS(on) = 4.6 mΩ at VGS = 4.5 V, ID = 15 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
Pin 1
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
„ Server
G1 D1 D1 D1
D1
S2 5
Q2
4 D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
S2 6
S2 7
G2 8
PHASE
3 D1
2 D1
Q1 1 G1
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25°C
TA = 25°C
Q1 Q2
25 25
±20 ±20
23 18
89
161a
88
181b
45
384
2.31a
1.01c
36
985
2.31b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
551a
1251c
551b
1251d
°C/W
Device Marking
Y8OA
K10OC
Device
FDMS3615S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3615S Rev.C6
1
www.fairchildsemi.com

FDMS3615S Datasheet
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25°C
ID = 10 mA, referenced to 25°C
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
IGSS
Gate to Source Leakage Current
VGS = 20 V, VDS = 0 V
Type Min Typ Max Units
Q1 25
Q2 25
V
Q1
Q2
18
16
mV/°C
Q1
Q2
1
500
μA
Q1 100 nA
Q2 100 nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 1.2 1.7 2.5
Q2 1.2 1.8 2.5
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25°C
ID = 10 mA, referenced to 25°C
Q1
Q2
-5
-6
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 16 A
VGS = 4.5 V, ID = 13 A
VGS = 10 V, ID = 16 A, TJ = 125°C
VGS = 10 V, ID = 18 A
VGS = 4.5 V, ID = 15 A
VGS = 10 V, ID = 18 A, TJ = 125°C
Q1
Q2
4.8 5.8
6.9 8.3
6.6 7.9
mΩ
2.5 3.4
3.6 4.6
3.4 4.1
gFS Forward Transconductance
VDD = 5 V, ID = 16 A
VDD = 5 V, ID = 18 A
Q1 63
Q2 84
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
Q1:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
1326 1765
2175 2895
pF
Q1
Q2
342 455
574 765
pF
Q1
Q2
78 115
118 180
pF
Q1 0.2 0.9 2.9
Q2 0.2 1.0 3.2
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg(TOT)
Total Gate Charge
Qg(TOT)
Total Gate Charge
Qgs Gate to Source Charge
Qgd Gate to Drain “Miller” Charge
Q1
VDD = 13 V, ID = 16 A, RGEN = 6 Ω
Q2
VDD = 13 V, ID = 18 A, RGEN = 6 Ω
VGS = 0V to 10 V
VGS = 0V to 4.5 V
Q1
VDD = 13 V,
ID = 16 A
Q2
VDD = 13 V,
ID = 18 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
7.7
9.5
15
19
ns
1.7
3
10
10
ns
19
24
34
49
ns
1.4
2.2
10
10
ns
19
31
27
43
nC
9
14
13
20
nC
3.6
5.7
nC
2.4
3.7
nC
©2011 Fairchild Semiconductor Corporation
FDMS3615S Rev.C6
2
www.fairchildsemi.com


Features Datasheet pdf FDMS3615S PowerTrench® Power Stage FDM S3615S PowerTrench® Power Stage 25V As ymmetric Dual N-Channel MOSFET August 2011 Features General Description Q1 : N-Channel „ Max rDS(on) = 5.8 mΩ at VGS = 10 V, ID = 16 A „ Max rDS(on) = 8.3 mΩ at VGS = 4.5 V, ID = 13 A Q2: N-Channel „ Max rDS(on) = 3.4 mΩ at V GS = 10 V, ID = 18 A „ Max rDS(on) = 4 .6 mΩ at VGS = 4.5 V, ID = 15 A „ Low inductance packaging shortens rise/fal l times, resulting in lower switching l osses „ MOSFET integration enables opt imum layout for lower circuit inductanc e and reduced switch node ringing „ Ro HS Compliant Pin 1 This device include s two specialized N-Channel MOSFETs in a dual PQFN package. The switch node ha s been internally connected to enable e asy placement and routing of synchronou s buck converters. The control MOSFET ( Q1) and synchronous SyncFET (Q2) have b een designed to provide optimal power e fficiency. Applications „ Computing „ Communications „ General Purpose Point of Load „ Notebo.
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