Timekeeping Controller. DS1384 Datasheet

DS1384 Controller. Datasheet pdf. Equivalent

Part DS1384
Description Watchdog Timekeeping Controller
Feature DS1384 Watchdog Timekeeping Controller www.maxim-ic.com FEATURES Keeps Track of Hundredths of Seco.
Manufacture Dallas
Datasheet
Download DS1384 Datasheet




DS1384
DS1384
Watchdog Timekeeping Controller
www.maxim-ic.com
FEATURES
Keeps Track of Hundredths of Seconds,
Seconds, Minutes, Hours, Days, Date of the
Month, Months, and Years with Leap Year
Compensation Valid Up to 2100
Watchdog Timer Restarts an Out-of-
Control Processor
Alarm Function Schedules Real-Time
Related Activities
Programmable Interrupts and Square-
Wave Outputs
Bytewide RAM-Like Access
50 Bytes of On-Board User RAM
Greater Than 10 Years Timekeeping and
Data Retention in the Absence of Power
with Small Lithium Coin Cells
Supports Up to 128k x 8 of External Static
RAM
All Timekeeping Registers and On-Board
RAM are Individually Addressable via the
Address and Data Bus
PIN CONFIGURATION
TOP VIEW
44
1
INTB/(INTB)
N.C.
A14
A12
A7
A6
A5
A4
A3
A2
A1
11
12
DS1384
MQFP
34
33
23
22
A15
VBAT1
WE
A13
A8
A9
A11
OE
A10
CE
OE
ORDERING INFORMATION
PART
TEMP RANGE
DS1384FP-12
0°C to +70°C
DS1384FP-12+
0°C to +70°C
VOLTAGE (V)
5.0
5.0
+ Denotes lead-free/RoHS-compliant device.
* A “+” anywhere on the top mark indicates a lead-free/RoHS-compliant device.
PIN-PACKAGE
44 MQFP
44 MQFP
TOP MARK*
DS1384FP
DS1384FP
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REV: 112105



DS1384
DS1384
DETAILED DESCRIPTION
The DS1384 watchdog timekeeping controller is a self-contained real-time clock, alarm, watchdog timer,
and interval timer that provides control of up to 128k x 8 of external low-power CMOS static RAM in a
44-pin quad flat-pack package. An external crystal and battery are the only components required to
maintain time of day and RAM memory contents in the absence of power. Access to all RTC functions
and the external RAM is the same as conventional bytewide SRAM. Data is maintained in the watchdog
timekeeper by intelligent control circuitry, which detects the status of VCC and write protects both
memory and timekeeping functions when VCC is out of tolerance. Timekeeper information includes
hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the
month is automatically adjusted for months with fewer than 31 days, including correction for leap year.
The timekeeper operates in either 12- or 24-hour format with an AM/PM indicator. The watchdog internal
timer provides watchdog alarm windows and interval timing between 0.01 seconds and 99.99 seconds.
The real time alarm provides for preset times of up to one week. All the RTC functions and the internal
50 bytes of RAM reside in the lower 64 bytes of the attached RAM memory map. The externally attached
static RAM is controlled by the DS1384 via the OER and CEO signals.
Automatic backup and write protection for an external SRAM is provided through the VCCO, CEO, and
OER pins. The lithium energy source used to permanently power the real time clock is also used to retain
RAM data in the absence of VCC power through the VCCO pin. The chip enable output to RAM (CEO) and
the output enable to RAM (OER) are controlled during power transients to prevent data corruption. The
DS1384 is a complete one-chip solution in that an external crystal and battery are the only components
required to maintain time of day memory status in the absence of power.
PIN DESCRIPTION
PIN NAME
1 INTB/(INTB)
2
3
4
5–12
25
27
28
29
30
33
40
N.C.
A14
A12
A7–A0
A10
A11
A9
A8
A13
A15
A16
FUNCTION
Interrupt Output B (Active High or Low). INTB outputs the alarm
(time of day or watchdog) that is not selected for INTA. This pin is
programmable high or low. Both INTA and INTB/(INTB) are open-
drain outputs. The two interrupts and the internal clock continue to run
regardless of the VCC level. However, it is important to ensure that the
pullup resistors used with the interrupt pins are never pulled up to a
value that is greater than VCC + 0.3V. As VCC falls below
approximately 3.0V, a power-switching circuit turns the lithium
energy source on to maintain the clock and timer data functionality. It
is also required to ensure that during this time (battery-backup mode)
the voltage present at INTA and INTB/(INTB) never exceeds VBAT.
At all times the current on each should not exceed +2.1mA or -1.0mA.
No Connection
Address Bus (Input). The address bus inputs qualified by CE, OE,
WE, and VCC are used to select the on-chip 64 timekeeping/RAM
registers within the memory map of the external SRAM controlled as
nonvolatile storage. When the qualified address bus value is within the
range of 00000H–0003FH, one of the internal registers is selected and
OER remains inactive. When the value is outside the range, OE is
passed through to OER.
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