Parallel EEPROM. AT28C010-12DK Datasheet

AT28C010-12DK EEPROM. Datasheet pdf. Equivalent

Part AT28C010-12DK
Description Space 1-MBit (128K x 8) Paged Parallel EEPROM
Feature Features • Fast Read Access Time – 120 ns • Automatic Page Write Operation – Internal Address and Da.
Manufacture ATMEL
Datasheet
Download AT28C010-12DK Datasheet

Features • Fast Read Access Time – 120 ns • Automatic Page W AT28C010-12DK Datasheet
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AT28C010-12DK
Features
Fast Read Access Time – 120 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
Low Power Dissipation
– 50 mA Active Current
– 10 mA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 5.104 Read/Modify Write Cycles @ Ground Level
– Data Retention: 10 Years
Operating Range: 4.5V to 5.5V, -55 to +125°C
CMOS and TTL Compatible Inputs and Outputs
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of (according to MIL STD 883 Method 1019):
– 10 kRads (Si) Read-only Mode when Biased
– 30 kRads (Si) Read-only Mode when Unbiased
JEDEC Approved byte-Wide Pinout
435 Mils Wide 32-Pin Flat Pack Package
AT2010-12DK Mil
Space 1-MBit
(128K x 8)
Paged Parallel
EEPROMs
AT28C010-12DK
Description
The AT28C010-12DK is a high-performance Electrically Erasable and Programmable
Read-Only Memory. Its one megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 120 ns with power dissipation of just 275 mW. When the device
is deselected, the CMOS standby current is less than 10 mA.
The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without
the need for external components. The device contains a 128-byte page register to
allow writing of up to 128 bytes simultaneously. During a write cycle, the address and
1 to 128 bytes of data are internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be
detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected
a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality in manufacturing. The
device utilizes internal error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available
to guard against inadvertent writes. The device also includes an extra 128 bytes of
EEPROM for device identification or tracking.
Rev. 4259E–AERO–02/11



AT28C010-12DK
Pin Configuration
Pin Name
A0 - A16
CE
OE
WE
I/O0 - I/O7
NC
FLATPACK
Top View
A16
A15
A12
A7
A6
NC
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 NC
30 WE
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Block Diagram
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
2 AT28C010-12DK
4259E–AERO–02/11





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