NAND E2PROM. TC58NVG0S3HBAI6 Datasheet

TC58NVG0S3HBAI6 E2PROM. Datasheet pdf. Equivalent


Part TC58NVG0S3HBAI6
Description 1G-BIT (128M x 8 BIT) CMOS NAND E2PROM
Feature TC58NVG0S3HBAI6 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1G BIT (128M  8 BIT) CMOS.
Manufacture Toshiba
Datasheet
Download TC58NVG0S3HBAI6 Datasheet


TC58NVG0S3HBAI6 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILI TC58NVG0S3HBAI6 Datasheet
Recommendation Recommendation Datasheet TC58NVG0S3HBAI6 Datasheet




TC58NVG0S3HBAI6
TC58NVG0S3HBAI6
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1G BIT (128M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG0S3HBAI6 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 128) bytes × 64 pages × 1024 blocks.
The device has a 2176-byte static registers which allow program and read data to be transferred between the register
and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit
(128 Kbytes + 8 Kbytes: 2176 bytes × 64 pages).
The TC58NVG0S3HBAI6 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed, making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
x8
2176 × 64K × 8
2176 × 8
2176 bytes
(128K + 8K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register
Read Cycle Time
25 µs max
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max
30 mA max
30 mA max
50 µA max
Package
P-VFBGA67-0608-0.80-001 (Weight: 0.095 g typ.)
8 bit ECC for each 512Byte is required.
© 2012-2018 Toshiba Memory Corporation
1
2018-12-14C



TC58NVG0S3HBAI6
PIN ASSIGNMENT (TOP VIEW)
12345678
A NC NC
NC NC NC
--------
--------
--------
--------
B NC WP ALE VSS CE WE RY/BY NC
--------
C NC NC RE CLE NC NC NC NC
D NC NC NC NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC NC NC
G NC I/O1 NC NC NC VCC
H NC NC I/O2 NC VCC I/O6 I/O8 NC
J NC VSS I/O3 I/O4 I/O5 I/O7 VSS NC
K NC NC NC
NC NC NC
PIN NAMES
I/O1 to I/O8
--------
CE
--------
WE
--------
RE
CLE
ALE
--------
WP
--------
RY / BY
VCC
VSS
NC
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Power supply
Ground
No Connection
TC58NVG0S3HBAI6
© 2012-2018 Toshiba Memory Corporation
2
2018-12-14C







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)