Piggyback Emulator. CDP68EM05D2 Datasheet

CDP68EM05D2 Emulator. Datasheet pdf. Equivalent


GE CDP68EM05D2
Product Preview
680S-Serles Microprocessors and Microcomputers
CDP68EM05D2
TERMINAL ASSIGNMENT
R""E"SET
TiiQ
NO
'"'''''''""""""""0
'"''""".
'''V"""ss
40-Lead Piggyback Package
CMOS High-Performance Silicon-Gate
8-Bit Micr~computer Piggyback Emulator
Features:
• All CDP68HC05D2 hardware and software features
• Un-multiplexed external address, data, and READ control lines
• Full 8K byte address space available (8064 bytes available externally)
• 96 bytes of on-Chip RAM, no ROM
• Direct interface to industry standard EPROMs
• 40-/ead piggyback package (1) with 28-ho/e socket for 2764 EPROM (2)
The CDP68EM05D2 Emulator device, a functional equivalent
to the CDP68HC05D2 microcomputer, is designed to permit
prototype development and preproduction of systems for
mask-programmed applications. Data and address bus, as
well as control signals are externally available.
In addition to this feature, the CDP68EM05D2 Emulator
differs from the CDP68HC05D2 in the following ways:
1) Memory locations which are occupied by ROM on the
CDP68HC05D2 are accessed as external locations with
the CDP68EM05D2 Emulator intended to interface to a
programmable ROM.
TCMP
PAO
PAl
PORT PA2
A PA3
I/O PA4
LINES PAS
PA6
PA7
DATA
DIR
REG
PBO
PBl
PORT PB2
B PB3
I/O PB4
LINES
PBS
PB6
P87
DATA
DIR
REG
-~... ~ 20
BUS
... CE
CONTROL
OSCl OSC2
INTERNAL
PROCESSOR CLOCK, iiESE'i
,--_ _ _ _ _ _=-2 iRa
ACCUMULATOR
8A
INDEX
REGISTER
X
CONDITION
CODE
S REGISTER CC
STACK
POINTER
6S
PROGRAM
COUNTER
HIGH PCH
PROGRAM
COUNTER
8 LOW PCL
CPU
CONTROL
CPU
ALU
DATA
DIR
REG
DATA
OIR
REG
SPI
SYSTEM
PCO
PCl
PC2
PORT
PC3 C
PC4 I/O
PCS LINES
PCB
PC7
TO TIMER SYSTEM
PD7
I!TOSCl (PDO)
TIMER
TOSC2 (POl) OSCILLATOR
MISO (PD2)
MOSl (PD3)
SPI
~K (PD4) SYSTEM
SS (PDS)
DESIGNATES EPROM
.. SOCKET
~~~~~~~~
* DATA BUS
~~~~~~~~~~~~~
*ADDRESS BUS
Fig. 1 - CDP68EM05D2 CMOS micrDcompu1er block diagram.
92CM-42534
File Number 1960
______________________________________________________________ 355


CDP68EM05D2 Datasheet
Recommendation CDP68EM05D2 Datasheet
Part CDP68EM05D2
Description CMOS High-Performance Silicon-Gate 8-Bit Microcomputer Piggyback Emulator
Feature CDP68EM05D2; Product Preview 680S-Serles Microprocessors and Microcomputers CDP68EM05D2 TERMINAL ASSIGNMENT R"".
Manufacture GE
Datasheet
Download CDP68EM05D2 Datasheet




GE CDP68EM05D2
6805-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68EM05D2
2) Mask-programmable options (CPU oscillator type and
external interrupt sense) are fixed in hardware. Only
one version of these options is available in the emulator.
These are:
a) CPU oscillator = crystal or ceramic resonator.
b) External interrupt request= negative edge and level
sensitive.
c) Start-up delay for power-on RESET or exit from
STOP mode = 4064 cycles.
Memory
The CDP68EM05D2 Emulator has a total address space of
8192 bytes. The CDP68EM05D2 Emulator has implemented
208 bytes of the address locations for 1/0 and internal RAM.
The remainder is available for external memory. The first
256 bytes of memory (page zero) is comprised of the I/O
port locations, timer locations, 48 bytes of external address
space and 176 bytes of RAM. The next 7936 bytes are
available to address external memory. The address map is
shown in figure2. The functions oltha internally addressable
peripherals can be found in the CDP68HC05D2 data sheet
File No. TSM-204.
'
Funcllonal Pin Delcrlptlon
The following list includes only those additional pins that
differ in function from those on the CDP68HC05D2
microcomputer. See the CDP68HC05D2 data sheet, File
No. TSM-204, for the remaining pins which are common.
AO-A12
DBO-BD7
OE
CE
-Address lines 0 through 12.
-Bidirectional 8-bit non-multiplexed data bus
with TTL inputs.
-Output Enable: An output signal used for
selecting external memory space. A low level
indicates when external ROM is being ac-
cessed. The Output Enable signal will not go
true, however, when addressing the 10 unused
locations in the 32 bytes of the 1/0 space even
though the address lines will be valid.
-Chip Enable: A status output which indicates
direction of data flow with respect to external
or internal memory space). A read of internal
memory or 1/0 will place data on the external
data bus. When addressing external memory,
this Signal in conjunction with OE, will enable
a READ access from a piggyback EPROM.
SOOOO
I/O
32 BYTES
0000--
PORTS
8 BYTES
0000---
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
$00
$01
$02
SOOI F
S0020
,
EXTERNAL
ADDRESS SPACE
128 BYTES
0031
0032
\
\
S009F
SODA0
0159
0160
\
RAM
96 BYTES
\
\
\
i. ~~~~SOOBF f - - - - - - -
SOOCO
\
\
STACK
SOOF F
64 BYTES 0255 \
S0100
0256 \
UNUSED
2 BYTES
SERIAL PERIPHERAL
INTERFACE
3 BYTES
UNUSED
5 BYTES
TIMER
10 BYTES
UNUSED 2 BYTES
SPECIAL PORT
CONTROL/
STAT REGISTER
PORT D DATA REGISTER
$03
PORT A DATA DIRECTION REGISTER
$04
PORT B DATA DIRECTION REGISTER
S05
PORT C DATA DIRECTION REGISTER
S08
PORT D DATA DIRECTION REGISTER
S07
UNUSED
S08
UNUSED
$09
SERIAL PERIPHERAL CONTROL REGISTER SOA
SERIAL PERIPHERAL STATUS REGISTER SOB
SERIAL PERIPHERAL DATA 1/0 REGISTER soc
UNUSED
SOD
UNUSED
$OE
UNUSED
SOF
,
EXTERNAL
ADDRESS SPACE
7936 BYTES
\
\ UNUSED
1 BYTE
\
0031
UNUSED
UNUSED
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
SID
$11
$12
$13
i$1 FEF
$IFFO
1
-
-
-
-
-
-
-
SPACE FOR
USER VECTORS
18 BVTES
$IFFF
8175
8176
8191
\
\
\
\
\
\
\
\
\
\
INPUT CAPTURE HIGH REGISTER
S14
INPUT CAPTURE LOW REGISTER
$15
OUTPUT COMPARE HIGH REGISTER
S16
OUTPUT COMPARE LOW REGISTER
S17
COUNTER HIGH REGISTER
$18
COUNTER LOW REGISTER
$19
ALTERNATE COUNTER HIGH REGISTER $IA
ALTERNATE COUNTER LOW REGISTER $IB
UNUSED
$IC
UNUSED
$ID
SPECIAL PORT CONTROL/STAT REGISTER $IE
UNUSED
$1 F
f . OE ACTIVE IN THIS SPACE
Fig. 2 - Address map.
92CM-42535
356 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___



GE CDP68EM05D2
________________ 680S-Serles Microprocessors and Microcomputers
CDP68EM05D2
IRQ (Ma,kable Interrupt Reque't)
Interrupt input which is ~tive edge and level sensitive.
Either type of inputto the fRU pin will produce the interrupt.
The MCU completes the current instruction before it
responds to the interrupt request. When the IRQ pin goes
low for at least one t.L.H as defined in the CDP68HC05D2
data sheet, a logic one Is latched Internally to signify that an
interrupt has been requested. When the MCU completes it's
current instruction, the interrupt latch is tested. If the
interrupt latch contains a logic one, and the interrupt mask
bit (I bit) in the condition code register is clear, the MCU
then begins the interrupt sequence. The IRQ Input requires
an external resistor to VDD for "wire-OR" operation.
OSC1,OSC2
A NAND gate Is connected between these two pads (OSC2
= output) for use as a crystal or ceramic resonator oscillator
with a STOP clock mode. The internal clocks are derived by
a divide-by-2 of the internal oscillator frequency (fole).
Alternatively, an external clock may be used by applying the
external clock signal to the OSC1 input with the OSC2 input
not connected.
ascI
I[ FETCH [ READ [ READ ['NWTERRITNEAL[ FETCH READ ['NTWERRINTAEL[FETCH \
ADDR::X::::JC::::X::::JC::::JC::::X::::)C::::X:::
OBO-D87 _r-"-JUr-,-<"-J -'-"\oJ
BUS DRIVERS DATA VALID
TURN ON
Fig, 3 - Typical cycle timing for the CDP6BEM05D2 emulator.
I--TCPL-I
csc 1
~TcPH-1
REAO CYCLE
i------TRC---
AO-A12 =:t=========~~=
92CS-42432
Fig. 4 - Control timing diagram for the CDP6BEM05D2 emulator,
________________________________________________________________ 357







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