DYNAMIC RAMS. UPD411A-1 Datasheet

UPD411A-1 RAMS. Datasheet pdf. Equivalent


NEC UPD411A-1
NEe Microcomputers, Inc.
NEe
Jl.PD411A
Jl.PD411A-1
Jl.PD411A-2
DESCR IPTION
4096 BIT DYNAMIC RAMS
The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The ,uPD411 A Family is designed using
dynamic circuitry which reduces the standby power dissipation.
Reading information from the memory is non·destructive. Refreshing is easily
II
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed whether
Chip Select is a logic high or a logic low.
FEATURES
Low Standby Power
• 4096 words x 1 bit Organization
• A single low·capacitance high level clock input with solid ±1 volt margins.
• Inactive Power 0.7 mW (Typ.)
• Power Supply +12, +5, -5V
• Easy System Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
• 22 pin Plastic Dual·in-Line Package
• Replacement for INTEL's 21078, TI's 4060 and Equivalent Devices.
• 3 Performance Ranges:
~PD411A
~PD411A·l
~PD411A·2
ACCESS TIME
300 ns
250 ns
200 ns
RfW CYCLE
470 ns
430 ns
400 ns
RMWCYCLE REFRESH TIME
65Uns
600ns
520 ns
2m.
2m.
2m,
PIN CONFIGURATION
VBB
Ag
A10
A11
Cs
DIN
DOUT
AO
"1
A2
VCC
Vss
AS
A7
AS
VOD
CE
NC
A5
A4
.4.3
WE
Rev/1
PIN NAMES
AO' All
AO-AS
CE
Address Inputs
Refresh Addresses
ChiD Enable
CS Chip Select
DIN Data Inpl..It
DOUT
WE
Data O"tput
Write Enable
VOD
Vce
VSS
Vas
INC
Power (+12V)
Powe, (+5V)
Ground
(Pow... -5V)
No Connection
19


UPD411A-1 Datasheet
Recommendation UPD411A-1 Datasheet
Part UPD411A-1
Description 4096-BIT DYNAMIC RAMS
Feature UPD411A-1; NEe Microcomputers, Inc. NEe Jl.PD411A Jl.PD411A-1 Jl.PD411A-2 DESCR IPTION 4096 BIT DYNAMIC RAMS.
Manufacture NEC
Datasheet
Download UPD411A-1 Datasheet




NEC UPD411A-1
,..,PD411A
CE Chip Enable.
A single extemal clock input is required. All read, write, refresh and read-modify-write
operations take place when chip enable input is high. When the chip enable is low, the
memory isin the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.
FUNCTIONAL DESCRIPTION
CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
AO-A11 Addresses
All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are pro-
vided on the chip to repuce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify·write cycle while the chip enable is high.
The data in terminal can be driven from standard TT L circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower-order-address inputs AO through AS or by addressing every row within any
2-millisecond period. Addressing any row refreshes all 64 bits in that row ..
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.
AO o--_~
AI
A20--_--I
Aa 0--_'"
A40--_--I
AS 0--_"'1
aw:
l>-
I>-
::>
'"
TIMING.
CE GENERATOR
CELL MATRIX
64 x 64
- - - - 0 Voo
------<I VCC
---oVss
---OVss
BLOCK DIAGRAM
...-~cs
t--~ WE
110
20



NEC UPD411A-1
fLPD411A
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to +70oe
Storage Temperature ............................... -55°C to +12Soe
Output Voltage CD .................................+20 to -0.3 Volts
All Input Voltages CD ...............................+20 to -0.3 Volts
Supply Voltage VDD CD .............................+20 to -0.3 Volts
Supply Voltage Vee CD .............................+20 to -0.3 Volts
Supply Voltage VsS CD . .
. .......................+20 to -0.3 Volts
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
CDNote: Relative to Vee.
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTER ISTICS
*Ta = 25°C
Ta = o°c to 70°C, Voo = +12V ± 10%, VCC = +5V ± 10%, Vee = -5V ± 10%, VSS = OV
LIMITS
PARAMETER
SYMBOL MIN. TYP. (]) MAX. UNIT
TEST CONDITIONS
II
Input Load Current
III
0.Q1
CE Input Load Current ILC
0.01
Output Leakage Current
for High Impedance State ILO
0.01
VOO Supply Current
during CE off
100 OFF
50
VOO Supply Current
during CE on
IOOON
35
Average VOO Current
IlP0411A
IlPD411A-l
IlP0411A-2
IOOAV
IOOAV
IOOAV
VSS Supply Current (2) ISS
VCC Supply Current
during CE off @
ICC OFF
38
38
38
5
0.01
Input Low Voltage
Input High Voltage
CE Input Low Voltage
CE Input High Voltage
Output Low Voltage
Output High Voltage
VIL
VIH
VILC
VIHC
VOL
VOH
-1.0
2.4
-1.0
VOO- 1
0
VOO
2.4
10 IlA
10 pA
±10 IlA
200 pA
50 mA
55 mA
55 mA
55 mA
100 pA
10 pA
0.6
VCC + 1
0.6
VOO + 1
0.40
VCC
V
V
V
V
V
V
VIN = VIL MIN to VIH MAX
VIN = VILC MIN to VIHC MAX
CE = VILC or CS = VIH
Vo = OV to 5.25V
CE = -1.0V to 0.6V
CE =VIHC, Ta = 25°C
Ta =25 C
Cycle Time = 470 ns
Cycle Time = 430 ns
Cycle Time = 400 ns
CE = VILC or 1% = VIH
IOL =3.2mA
IOH =-2.0 mA
CAPACITANCE
Notes:
(]) Typical values are for Ta = 25°C and nl'minal power supply voltages.
(2) The ISS current is the sum of all leakage currents.
@ During CE on VCC supply current is dependent on output loading.
Ta = o°c to 70°C. VOO = 12V ± 10%. VCC =+5V ± 10%. VBB = -5V ± 10%. Vss = OV
PARAMETER
LIMITS ....
TEST
SYMBOL MIN. TYP. MAX. UNIT CONDITIONS
Address Capacitance
es Capacitance
DIN Capacitance
DOUT CapaCitance
WE Capacitance
CE Capacitance
CAD
CCS
CIN
COUT
CWE
CCE1.
CCE2
6 pF VIN = Vss
6 pF VIN =VSS
6 pF VIN =Vss
7 pF VOUT= VSS
7 pF VIN = Vss
27 pF VIN ~ Vss
22 pF VIN -VOO
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