ACCESS MEMORY. UPD2118-3 Datasheet

UPD2118-3 MEMORY. Datasheet pdf. Equivalent


NEC UPD2118-3
NEe Microcomputers, Inc.
16384 x 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
NEe
,uPD2118
,uPD2118-2
JI. PD2118-3
[~OO~[~~~~ffirnW
DESCR IPTION
ThepPD2118 is a single +5V power supply, 16384 word by 1 bit Dynamic MOS RAM.
The IlPD2118 achieves high speed with low power dissipation by the use of single tran·
sistor dynamic storage cell design and advanced dynamic circuitry. This circuit design
results in the minimizing of current transients typical of dynamic RAMS. This in turn
II
results in high noise immunity of the IlPD2118 in a system environment. By using a
multiplexing technique, the IlPD2118 can be packaged in an industry standard 16·Pin
Dip utilizing 7 address input pins for the 14 address bits required. The two 7 bit address
words are referred to as the ROWand COLUMN address. Two TTL clocks, ROW address
strobe (RAS) and COLUMN address strobe (CAS") latch these two words into the
IlPD2118. Non·critical timing requirements for RAS and CAS permit high systems per·
formance without placing difficult constraints upon the multiplexing control circuitry.
The IlPD2118 has a three·state output controlled by CAS, independent of RAS. Follow·
ing a valid read or read·modify·write cycle, data will be held in the output by holding
CAS low. Returning CAS to a high state will result in the data out pin reverting to the
high impedance mode. Use of this CAS controlled output means that the IlPD2118 can
perform hidden refresh by holding CAS low to maintain latch data output while using
RAS to execute RAS·only·refresh cycles.
The use of single transistor storage cell circuitry ~equires that data be periodically
refreshed. Refreshing can be accomplished by performing RAS·only·refresh cycles,
hidden refresh cycles or normal read or write cycles on each of the 128 address com-
binations of AO through A6 during a 2 ms period. The write cycle will refresh stored
data on all bits of the selected row, except that the bit which is addressed will be mod·
ified to reflect the data input.
FEATURES
Single+5VSupply,±10%Tolerance
• Low Power: 138 mW Max Operating
16 mW Max Standby
• Low VDD Current Transients
• All Inputs, Including Clocks, TTL Compatible
•• Non·Latched Output is Three·State
• RAS·Only·Refresh
• 128 Refresh Cycles Required
• Page Mode Capability
• CAS Controlled Output Allows Hidden Refresh
PIN
IlPD2118
IlPD2118·2
IlPD2118·3
ACCESS TIME
150 ns
120 ns
100 r1'S
RIW CYCLE
320 ns
270 ns
235 ns
RMWCYCLE
410 ns
345 ns
295 ns
PIN CONFIGURATION
NC
DIN
WE
RAS
AO
A2
Al
Vss
CAS
DOUT
A6
A3
A4
AS
NC
An·All
CAS
DIN
DOUT
WE
RAS
VDD,
Vss
PIN NAMES
ADDRESS INPUTS
COLUMN ADDRESS STROBE
DATA IN
DATA OUT
WRITE ENABLE
ROW ADDRESS STROBE
POWER (+SV)
GROUND
37


UPD2118-3 Datasheet
Recommendation UPD2118-3 Datasheet
Part UPD2118-3
Description 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY
Feature UPD2118-3; NEe Microcomputers, Inc. 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY NEe ,uPD2118 ,uPD2118-2 JI..
Manufacture NEC
Datasheet
Download UPD2118-3 Datasheet




NEC UPD2118-3
,uPD2118
64 x 128 CELL
MEMORY ARRAY
128 SENSE
AMPLIFIERS
1 OF 64 COLUMN
DECODERS
64 x 128 CELL
MEMORY ARRAY
BLOCK
DIAGRAM
1 OF 2
I/O
GATING
OUTPUT
BUFFER
DOUT
Ambient Temperature Under Bias .. .
Storage Temperature ........... .
Voltage On Any Pin Relative to VSS .
Data Out Current
Power Dissipation ............. .
. -10°C to +80°C
-65°C to +150°C
. -2.0 to +7.5V
. .50mA
....... 1.0W
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or at any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliabiiity.
ABSOLUTE MAXIMUM
RATINGS*
38



NEC UPD2118-3
J'PD2118
DC CHARACTERISTICS
READ, WRITE, AND
READ MODIFY WRITE
CYCLESCD
Tam O°C to 70°C, Veo"" 5V:t 10%. VSS= av, unless otherwise noted.
PARAMETER
SYMBOL
LIMITS
MIN MAX UNIT
TEST CONOITIONS
NOTES
Input Load Current
Output Leakage Current
for High Impedance State
Veo Supply Current
(Standby)
'll
'LO
'DOl
10 "A VIN = VSS to Veo
10 "A Chip Deselected ~at
VIH,VOUT= Oto5.5V
3 mA CAS and RAS at V'H
VOO Supply Current
(Operating)
"P02118·3
j.lPD2118·2
"P02118·0
VOO Supply Current
(RAS-Only Cycle)
"P02118·3
"P02118·2
,.,.PD2118-0
VoO Supply Current Page
Mode, Maximum tpc
Minimum teAS
"P02118-3
"P02118·2
jJ.P0211S-Cl
VOO Supply Current
(Standby. Output Enabled)
1002
1002
'002
1003
'003
'003
'004
10D4
'004
1005
25 mA
22 mA TRC = TRC Min
22 mA
20 mA
18 mA
18 mA
TRC= TAC Min
®
® II
20 mA
17 mA
15 mA
®
®4 mA CAS at VIL. RAS at VIH
Input Low Voltage
V,L
-2.0
0.8
V
Input High Voltage
V,H
2.4 7.0
V
O':!tput low Voltage
VOL
0.4 V IOL =4.2 rnA
Output High Voltage
VOH
2.4
IOH =-SmA
<DNotes:
@
All voltages referenced to VSS.
too is dependent on output loading when the device outPut is selected. Specified
100 Max Is measured with the output open.
CAPACITANCE CD
T a ; 25°C, VDD ; 5V ± 10%, VSS ; OV, unless otherwise noted.
SYMBOL
PARAMETER
TYP MAX
UNIT
Cll
Address Data In
3
5
pF
Cl2 RAS WE
4 7 pF
Cl3 CAS
6 10
pF
CO Data Out
4 7 pF
NOTES: CD Capacitance measured with Boonton meter or effective capacitance
calculated from the Equation C; I~T/~V with ~V equal to 3V
and power supplies at nominal levels.
39







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