CMOS RAM. UPD6514 Datasheet

UPD6514 RAM. Datasheet pdf. Equivalent


NEC UPD6514
NEe Microcomputers, Inc.
NEe
fL PD444/6514
fL PD444/6514·1
fL PD444/6514·2
fL PD444/6514·3
1024 x 4 BIT STATIC CMOS RAM
OESCR IPTION
The /JPD444/6514 is a high-speed, low power silicon gate CMOS 4096-bit static RAM
organized 1024 words by 4 bits_ It uses DC stable (static) circuitry throughout and
therefore requires no clock or refreshing to operate_ Data access is particularly simple
since address setup times are not required. The data is read out nondestructively and
has the same polarity as the input data. Common input/output pins are provided.
CSCS controls the power down feature_ In less than a cycle time after goes high -
deselecting the /JPD444/6514 - the part automatically reduces its power requirements
and re~ins in this low power standby mode as long as Cs is high. There is no mini-
mum CS high time for device operation, although it will determine the length of time
in the power down mode. When CS goes low, selecting the /JPD444/6514, the
/JPD444/6514 automatically powers up_
The /JPD444/6514 is placed in an 18-pin plastic package for the highest possible
density _It is directly TTL compatible in all respects: inputs, outputs, and a single
+5V supply_ The /JPD444/6514 is pin-compatible with the /JPD2114L NMOS Static
RAM.
Data retention is guaranteed to 2 volts on all parts. These devices are ideally suited
for low power applications where battery operation or battery backup for non-
volatility are required.
FEATU RES
Low Power Standby - 5 /JW Typ.
• Low Power Operation
• Data Retention - 2.0V Min_
• Capability of Battery Backup Operation
• Fast Access Time - 200-450 ns
• Identical Cycle and Access Times
• Single +5V Supply
• No Clock or Timing Strobe Required
• Completely Static Memory
• Automatic Power-Down
• Directly TTL compatible: All Inputs and Outputs
• Common Data Input and Output using Three-State Outputs
• Replacement for /JPD2114L and Equivalent Devices
• Available in a Standard 18-Pin Plastic Package
PIN CONFIGURATION
AS
AS
A4
Aa
AO
A1
A2
CS
GND
Vee
A7
AS
Ag
1/01
1/02
I/0a
1/04
WE
PIN NAMES
AO-A9
WE
CS
1/0 1-1/0 4
VCC
GND
Add ress Inputs
Write Enable
Chip Select
Data Input/Output
Power (+5V)
Ground
Rev/l
89


UPD6514 Datasheet
Recommendation UPD6514 Datasheet
Part UPD6514
Description 1024 x 4 BIT STATIC CMOS RAM
Feature UPD6514; NEe Microcomputers, Inc. NEe fL PD444/6514 fL PD444/6514·1 fL PD444/6514·2 fL PD444/6514·3 1024 x .
Manufacture NEC
Datasheet
Download UPD6514 Datasheet




NEC UPD6514
}J. P0444/6514
WRITE CYCLE ® @ ®
---..
-ADDRESS
.
twe
tew
\ -; I I I I I I I
OOUT
_tAS_
tAW
f---twP-
\ ..,
tow
---tWR
tDH
/"
I
DATA IN
VALID
twz I
~
~
~.
.I] ~HIGH IMPEDANCE
/
""
CDNotes:
We IS high for Read Cycles.
® Device IS contlnuouslV selected, ES = VIL
@ Address valid prior to or cOincident with CS tranSition low.
@ If the CS low transition occurs simultaneously with the WE low transition, the
output buffers remain in a high Impedance state.
® WE must be high during all address transitions.
® IWp is measured from the latter of CS or WE going tow to the earher of Cs or WE
going high.
LOW VCC OATA RETENTION
DATA
Vee -------:--'"11
ov - - - - - - - - - - - - - - - - - - - - - - -
---------A----------~
PACKAGE OUTLINE
J.LPD444/6514C
Plastic·
ITEM
A
C
0
F
G
H
M
MILLIMETERS
23.2 MAX.
1.44
2.54
0.45
20.32
1.2
2.SMIN.
0.5 MIN.
4.6 MAX.
5.1 MAX.
7.62
6.7
0.25
INCHES
0.91 MAX.
0.055
0.1
0.02
0.8
0.05
0.1 MIN.
0.02 MIN.
0.18 MAX.
0.2 MAX.
0.3
0.26
0.01
444/6514DSREV1·12-80-CAT
90



NEC UPD6514
AC CHARACTERISTICS
LOW VCC DATA
RETENTtON
CHARACTERISTICS
}J. PD444/6514
Ta" -40 C to "'85 C; Vee = +5V • 10% unless otherwise noted.
PARAMETER
I LIMITS
I
44416514·3 444/6614·2 44416514·1 444/6514
SYMBOL MIN[MAXIMINtMAXIMIN IMAX IMIN (MAX I UNIT
REAOCVCLE
TEST CONDITIONS
Read Cvcle
Address Access Time
Ctup Select Access Time 1
Chip Select Access Time Q)
Output Hold from Address Change
Chip Selection to Output In Low Z
Chip Deselectlon to Output In High Z
'Re
'AA
tACSl
tACS2
'0"
'LZ
'HZ
200 2SO 300 4SO
200 2SO 300 4SO
200 2SO 300 4SO
2SO 300 3SO 500
50 SO SO SO
20 20 20 20
60 70 80 100
WRITE CYCLE
Input Pul•• Levels:
"'0.8 10 +2.4 Volts
Input Alse and FaU
Time,: 10n5
Input and Output Timing
Levels: 1.S Volt
Output load: 1 TTL
Gete and Cl • 100 pF
Wrl1e Cycle Time
Chip Selection to End of Write
Address Vahd to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled 10 Output in High Z
Output Active from End of Write
'we
'ew
'AW
'AS
'WP
'WR
'OW
'OH
'wz
'OW
200 2SO 300 4SO
180 230 2SO 3SO
180 230 2SO 3SO
0
180 210 230 300
000 0
120 140 ISO 200
00
60 70 80 100
Input Pulse levels:
+0.8 to +2.4 Vohs
Inp!,it Rise and Fell
Times' 10n5
Input and Output Timing
Levels: 1.5 Vall
Output Load: 1 TTL
Gate and Cl = 100 pF
Notes, CD Ch,p deselected for greater than 100 ns prior to selection,
a~ Chip deselected for a hnlte time that IS less than 100 ns prior to selection, (If the deselect time 15 ns, the chip is by definitiOn
selected and access occurs according to Read Cycle No.1,)
II
r = --40" C to +85' C
P,u'c-, r.JIETER
~.~~
Dal'" ; .. •.' Supply
VOI\d:Y_
SYMBOL
VCCDR
Data Retention Supply
Current
ICCDR
Chip Deselect to Data
Retention Time
tCDR
Operation Recovery
Time
tR
CDNote: tRC = Read Cycle Time
LIMITS
MIN
TYP MAX
2.0
0.01 10
0
tRCQ)
UNIT
V
jJ.A
ns
ns
TeST CONDITIONS
CS = VCC,VIN = VCC
to GND
VCC - 3V, CS = VCC
VIN = VCC to GND
TIMING WAVEFORMS
ADDRESS
READ CYCLE G) @
Dour
PREVIOUS DATA VALID
xx
DATA VALID
i i ---1-----READCYCLE G).@
CS I - -_- -_ ' R C -
:ACS
'LZ
!--'HZ
°OUT
HIGH IMPEDANCE
DATA VALID
HIGH
IMPEDANCe:
91







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