CMOS RAM. UPD445L-1 Datasheet

UPD445L-1 RAM. Datasheet pdf. Equivalent

UPD445L-1 Datasheet
Recommendation UPD445L-1 Datasheet
Part UPD445L-1
Description FULLY DECODED 4096 STATIC CMOS RAM
Feature UPD445L-1; NEe Microcomputers, Inc. NEe fLPD445L fLPD445L·1 FULLY DECODED 4096 STATIC CMOS RAM DESCRIPTION .
Manufacture NEC
Datasheet
Download UPD445L-1 Datasheet



NEC UPD445L-1
NEe Microcomputers, Inc.
NEe
fLPD445L
fLPD445L·1
FULLY DECODED 4096 STATIC CMOS RAM
DESCRIPTION
The ~PD445L is a very low power 4,,096 bit (1024 words by 4 bits) static RAM fabricated
with NEC's complementary MOS (CMOS) process, It has two chip enable inputs (CE1,
CE2). Minimum standby current is drawn when CE1 is at a high level, while inhibiting
I I 'all address and control line transitions or, unconditionally when CE2 is at a low level.
This device ideally meets the low power requirements of battery operated systems and
battery back-up systems for non-volatility of data.
The ~PD445L uses fully static circuitry requiring no clocking. Output data is read out
non-destructively by placing a high on the R/W pin and has the same polarity as input
data. All inputs and outputs are directly TTL compatible. The device has common
input/output data busses and an OD (Output Disable) pin for use in common I/O bus
systems.
". The ~PD445L is guaranteed to retain data with the power supply voltage as low as 2.0
volts.
FEATURES
Single +5V Power Supply
• Ideal for Battery Operation
• Low Standby Power fllr Dat,a Retention
• Simple Memory Expansion - Chip Enable Inputs
• Access Time - 650 ns Max. {J,tPD445L)
4.50 ns Max. (~PD445L-1)
• Directly TTL Compatible - All Inputs and Outputs
• Common Data Input and Output
• Static CMOS - No Clock or Refreshing Required
• 20 Pin Dual-In-Line Plastic Package
PIN CONFIGURATION
A3
A2
A,
AO
AS
As
A7
GNO
I/O,
1/°2
VCC
A4
R/W
eE,
00
CE2
A8
Ag
1/°4
1/03
PIN NAMES
Ao-Ag
00
R/W
CE,
CE2
1/0,-1/°4
VCC
GNO
Address Input
Output Disable
Read/Write.
Chip Enable'
Chip Enable 2
Data Input/Output
Power Supply
GrO\lnd
OPERATION MODES
CE, CE2 00
,0 0
, ,0
Others
Chip
Selected
Non-Selected
Output Mode
Data Out
High Impedance
93



NEC UPD445L-1
,uPD445L
ADDRESS
BUFFER
X
DECODER
MEf\10HY
CELL
MATRIX
64 ~ 64
BLOCK DIAGRAM
Operating Temperature .....
.......... OoC·to +70·C
Storage Temperature.
. ...... -40°C to +12Soc:;
All Output Voltages.
-0.3 to VCC +0.3 Volts
All Input Voltages ..
. . . . . . . . . . . . . . . . . . . -0.3 to Vec +0.3 Vol...
Supply Voltage VCC
. . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +7 Velts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is. stress rating only and functional operation of the device at these or
an'y other conditions above those indicated in the operational sections of this specification i. not
implied. Exposure to absolute maximum rating conditions for extended periods may affect deviae
reliability.
*Ta = 25°C
AISOLun MAXIMUM
I'IATINGS*
PARAMETER
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Current High
Input Leakage
Current Low
Output Leakage
Current High
Output Leakage
Current Low
Supply Curtent
Supply Current
StandbY Current
SYMBOL
V'H
V'L
VOHl
VOH2
VOL
ILiH
LIMITS
MIN TYP
MAX
UNIT
+2.2
-0.3
+2.4
+3.5
Vee
+ 0.65
+ 0.4
V
V
V
V
V
+ 1.0 ~A
'LIL
- 1.0 ~A
'LOH
+ '.0 ~A
'LOL
'.0 ~A
'ce,
'2 25 rnA
'CC2
leCL
'6 30 rnA
40 ~A
TEST
CONDITIONS
IOH - --1.0 rnA
'OH' 'OO~A
IOL '" +2.0 rnA
V, . Vee
V, . OV
ee, ,Vo' Vee.
2.2V
ee, ,VO' OV.
2.2V
Outputs Open
ee,VI ::: Vee except
<: O.65V
Outputs Open
VI '" 2.2V except
EE, ~ O.65V
V, ' 0 to 5.2SV
Except eE2 :E;; O.2V
'f DC CHARACTEf'lISTICi
94



NEC UPD445L-1
JLPD445L
CAPACITANCE
Ta 1 MHz
PARAMETER
Input Capacitance
Output Capac itance
SYMBOL
Cr
Co
LIMITS
MIN TYP MAX
58
8 12
TEST
UNIT CONDITIONS
pF VI = OV
pF ~ Vo = OV
AC CHARACTERISTICS
READ CYCLE
Ta = o°c to +70°C- VCC" +5V ± 10%
PARAMETER
SYMBOL
LIMITS
445L
445L-'
MIN MAX MIN MAX
Read Cycle Time
Access Time
tRC
tA
650
650
450
450
Chip Enable
ICEll to Output
tCOl
600 400
Chip Enable
ICE21 to Output
tC02
700 500
Output Enable
to Output
too
350 250
Output Disable
100 I to Floating
tDF
0 150
0 130
Data Output
Hold Time
tOHl
0
0
Chip Disable
to Floating
tOH2
0
0
Address Rise
and Fall Time
tr
tf
300 300
UNIT
ns
ns
ns
IIITEST
CONDITIONS
I nput Voltage Levels
V = +0.65 to +2.2V
Input Rise Time
ns
20 ns
Input Fall Time
ns
20 ns
Timing Measurement
ns
Reference Level 0:
+1.5V
ns
Output Load
1 TTL+ 100pF
ns
For Address change
ns
during Chip Enabled
WRITE CYCLE
Ta = O°C to +70°C; VCC = +5V ± 10%
LIMITS
PARAMETER
SYMBOL
445L
MIN MAX
445L·'
MIN MAX
Write Cycle Time
Address Setup
Time
twc
tAW
650
150
450
130
Chip Enable
ICE 11 to Write
End
tCWl
550
350
Chip Enable
ICE21 to Write
End
tCW2
550
350
Data Setup Time
Data Hold Time
Write Pulse Width
Address Hoid
Time
tow
tDH
twp
tWR
400
100
400
50
250
50
250
50
Output Disable
Setup Time
tDS
150
130
Address Rise
and Fall Time
tr
tf
300 300
UNIT
ns
ns
TEST
CONDITIONS
Input Voltage Levels
V I = +0.65 to +2.2V
ns Input Rise Time
20 ns
ns Input Fall Time
20 ns
ns
ns Timing Measurement
ns Reference Level :::
+~.5V
ns
ns
ns For Address change
during Chip Enabled
95







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