4-BIT MICROPROCESSOR. UPD7500 Datasheet

UPD7500 MICROPROCESSOR. Datasheet pdf. Equivalent


NEC UPD7500
NEe Microcomputers, Inc.
4-81T MICROPROCESSOR
,uPD750X EVALUATION CHIP
DESCR IPTI ON
FEATURES
PIN CONFIGU~ATION
The !,PD7500 is a !,COM-75 4-bit microprocessor with a 256 x 4 RAM, a programmable 8-bit
timer/event counter, and 5 vectored, prioritized interrupts. It is capable of addressing 8,192 bytes
of external memory, and also functions as the prototype Evaluation Chip for the ,uPD750X family
of 4--bit single chip microcomputers. The ,uPD7500 is manufactured with a low-power-consumption
CMOS process, allowing use of a single power supply between 2.7 and 5.5V, and providing pro·
grammable power-down capability. It has 46 I/O lines, organized into eight 4-bit parallel ports,
one 14-bit parallel address/instruction port, and one 8-bit serial port. The ,uPD7500 executes 102
instructions of the ,uCOM-75 instruction set, and it is available in a 64 pin quad-in-line package.
• 4-Bit Microprocessor
• Evaluation Chip for !'PD750X Family of 4-Bit Single Chip Microcomputers
• Addresses up to 8,192 Bytes of External Memory
• 256 x 4 Bit RAM
• 10MS Instruction Cycle Time
• 102 Powerful Instructions
- Table Look-up Capability with LHLT and LAMTL instructions
- Indirect indexed addressing with CALT instruction
• RAM Stack
• Extensive I/O Capability
One 4-8it Input Port
Two 4-Bit Output Ports
Four 4·Bit I/O Ports, of which two are 8-Bit Byte Accessible
One 4-Bit I/O Port with Output Strobe
One 14·Bit Address/Instruction Port
One 8-Bit Serial I/O Port
• Programmable 8-Bit Timer/Event Counter with Crystal Clock Generator
• Vectored, Prioritized Interrupts
- 3 External
- 2 Internal (Timer and Serial I/O)
• Programmable Power-Down Operation with HA LT and STOP Instructions
• Built-In System Clock Generator
• Built-In Reset Circuitry
• Single Power Supply, Variable from 2.7V to 5.5V
• CMOS LSI
• 64-Pin Quad-In-Line Package
x,
X,
TEsT
BUSS
BUS9
BUS10
BUS11
BUS12
BUS;3
'40
'4,
'4,
'43
'50
'5,
'5,
'53
'60
'6,
'6,
'63
"0
''""
"3
tNT,
INTO
INT2
AESET
CL,
CL,
VOO
tL PD
7500
Vss
BUS7
BUS6
BUS5
BU S4
SU S 3
BU S2
BUS,
BUSO
P13
P1,
P1,
P10
ill
CsQ"O'T
LCD CL
P'S'EN
P20/STB
P2,/PTOUT
'"
"3
P03/S1
P02JSO
PO,/Sci<
'00
NC
ALE
Do"UT
"3
''""
'30
BUSO-BUS,3
'00
PO,/SCK
P02/S0
P03/S1
P'O·P1 3
P20/STB
P2, /PTOUT
P20·P23
P30·P33
P40·P43
P50·P53
P~O·~63
P70·P73
INTO
INT,
INT2
Cl" CL2
Xl, X2
ALE
CSOUT
DOU
LCD CL
PSEN
STB
AESET
VDD
VSS
TES
NC
PIN NAMes
Address/Instruction Bus
Input Port 00
Input Port O,/Serlal Clock
Input Port 02/Serial Output
Input Port 03/Serlallnput
Input/Output Port 1
Output Port 20/Pon 1 Strobe Output
Output Port 2,/Tlmer OutpUt
Output Port 2
Output Port 3
Input/Output POrt 4
Input/Output Port 5
Input/Output Port 6
Input/Output Port 7
Interrupt InputO
Interrupt Input 1
Interrupt Input 2
System Clock Input, Output
Crystal Clock Input, Output
Addrass LATCH ENABLE
Chip Select Output
LCD Clock OutPut
Program Store ENABL.E
Strobe'
Aelet
Power Supply Positive
Ground
Factory Telt Pin
No Connection
II
237


UPD7500 Datasheet
Recommendation UPD7500 Datasheet
Part UPD7500
Description 4-BIT MICROPROCESSOR
Feature UPD7500; NEe Microcomputers, Inc. 4-81T MICROPROCESSOR ,uPD750X EVALUATION CHIP DESCR IPTI ON FEATURES PIN .
Manufacture NEC
Datasheet
Download UPD7500 Datasheet




NEC UPD7500
JLPD7500
BLOCK DIAGRAM
.lot,Loll.
ITEM
A
B
C
0
E
F
G
I
J
K
L
M
Ceramic
MILLIMETERS
41.5
1,05
2.54
0.5 ± 0.1
39.4
1.27
5.4 MIN
2.35 MAX
24.13
19.05
15.9
0.25 ± 0.05
I'NCHES
1.634 MAX
0.042
0.1
0.2 ± 0.004
1.55
0.05
0.21 MIN
0.13 MAX
0.95
0.75
0.626
0.01 ± 0.002
238
PACKAGE OUTLINE
~1"075(J()B
7!!iOODS-10-80-CAT







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