COMMUNICATIONS INTERFACE. UPD8251 Datasheet
NEe Microcomputers, Inc.
PROGRAMMABLE COMMUNICATION INTERFACES
The}.lPD8251 and}.lPD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters (USARTs) are designed for microcomputer systems data communications.
The USART is used as a peripheral and is programmed by the 8080A or other
processor to communicate in commonly used serial data transmission techniques includ·
ing IBM Bi-Sync. The USART receives serial data streams and converts them into
parallel data characters for the processor. While receiving serial data, the USART will
also accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors and control signals such as TxE and SYNDET, is available
to the processor at any time.
• Asynchronous or Synchronous Operation
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (}.lPD8251 A)
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
• Baud Rate (1X Mode) - DC to 56K Baud (}.lPD8251)
- DC to 64K Baud (}.lPD8251A)
• Full Duplex, Double Buffered Transmitter and Receiver
• Parity, Overrun and Framing Flags
• Fully Compatible with 8080A/8085/}.lPD780 (Z80TM)
• All Inputs and Outputs are TTL Compatible
• Single +5 Volt Supply, ±10%
• Separate Device Receive and Transmit TTL Clocks
• 28 Pin Plastic DIP Package
• N-Channel MOS Technology
PIN CONFIGURATION 02
Data Bus 18 bitt)
Control or Data is to be Written or Read
And Data Command
Write Data or Control Command
Clock Pulse (TTL!
Transmitter Ctock (TTL)
Rewlve, Clock (TTL)
Receiver Ready (has character for 8080)
Transmitter Readv (readv for char. from 80an
O.t. Set Rudy
Data Terminal Ready
Sync Detect/Break Detect
Requillt to Send Oat.
CI••r 10 Send Data
+5 V04t Supply
TM: Z80 is a registered trademark of Zilog.
The pPDB251 and pPDB251 A Universal Synchronous/Asynchronous Receiver/
Transmitters are designed specifically for BOBO microcomputer systems but work with
most B-bit processors. Operation of the pPDB251 and pPDB251A, like other I/O devices
in the BOBO family, are programmed by system software for maximum flexibility.
In the receive mode, the pPD8251 or pPDB251A converts incoming serial format data
into parallel data a'nd makes certain format checks. In the transmit mode, it formats
parallel data into serial form. The device also supplies or removes characters or bits that
are unique to the communication format in use. By performing conversion and format-
ting services automatically, the USART appears to the processor as a simple or "trans-
parent" input or output of byte·oriented parallel data.
The pPDB251A is an advanced design of the industry standard B251 USART. It
operates with a wide range of microprocessors, including the B080, B085, and
pPD7BO (ZBOTM). The additional features and enhancements of the pPDB251A over
the pPDB251 are listed below.
pPD8251A FEATURES AND
1. The data paths are double-buffered with separate I/O registers for control, status,
Data In and Data Out. This feature simplifies control programming and min-
imizes processor overhead.
2. The Receiver detects and handles "break" automatically in asynchronous
operations, which relieves the processor of this task.
3. The Receiver is prevented from starting when in "break" state by a refined Rx
initialization. This also prevents a disconnected USART from causing unwanted
4. When a transmission is concluded the TxD line will always return to the marking
state unless SBR K is programmed.
5. The Tx Disable command is prevented from halting transmission by the Tx
Enable Logic enhancement, until all data previously written has been trans-
mitted. The same logic also prevents the transmitter from turning off in the mid-
dle of a word.
6. Internal Sync Detect is disabled when External Sync Detect is programmed. An
External Sync Detect Status is provided through a flip-flop which clears itself
upon a status read.
7. The possibility of a false sync detect is minimized by:
ensuring that if a double sync character is programmed, the characters be
clearing the Rx register to all Logic 1s (VOH) whenever the Enter Hunt com-
mand is issued in Sync mode.
B. The RD and WR do not affect the internal operation of the device as long as the
/-lPDB251A is not selected.
9. The pPDB251A Status can be read at any time, however, the status update will
be inhibited during status read.
10. The pPDB251A has enhanced AC and DC characteristics and is free from
extraneous glitches, providinll higher speed and improved operating margins.
11. Baud rate from DC to 64K.
C/O RD WR CS
0 0 10
pPD8251/pPDB251A ~ Data Bus
Data Bus ~ pPDB251!W'DB251A
Status ~ Data Bus
Data Bus ~ Control
Data Bus ~ 3-Stcte
TM:Z80 is a registered trademark of Zilog.
Ali Output Voltages.
All Input Voltages
Supply Voltages ...
. . . - 0° C to +70° C
-65°C to +125°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause perr:'anent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indica'ted in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
*Ta = 25°C
Ta = o'e to 70'e; Vee = 5.0V ± 10%; GND = OV.
SYMBOL MIN TYP MAX MIN MAX UNIT
Input Low Voltage
O.B 0.5 O.B V
Input High Voltage
Output Low Voltage
"PDB251 : IOL = 1.7 mA
"POB251A: IOL = 2.2 mA
Output High Voltage
"POB251 : IOH = -10e"A
"POB251A: IOH =-400 "A
Data Bus Leakage
10 10 "A VOUT = Vce
Input Load Current
Power Supply Cur,rent ICC
10 "A At 5.5V
"PDB251A: All Outputs ::
te = 1 MHz