Audio DSP. AK7782 Datasheet

AK7782 DSP. Datasheet pdf. Equivalent


AKM AK7782
[AK7782]
AK7782
Dual Audio DSP with 24bit 5ch ADC & SRC
GENERAL DESCRIPTION
The AK7782 is an audio digital signal processor with integrated 24bit 5ch ADCs, an 8:2 stereo input
selector and sample rate converters that support 2ch inputs and the frequency up to 96kHz. The ADC
supports wide range of sampling frequency from 7.35kHz to 96kHz. Two integrated audio DSPs have
high performance processing speed of 2560step/fs (at 48kHz sampling), and two 6k-word delay RAMs
allow surround processing, time alignment adjusting and FIR filtering. As the AK7782 is a RAM based
DSP, it is programmable for various user requirements. It is housed in a 100pin LQFP package.
FEATURES
[DSP1/DSP2]
Word Length: 28-bits
Instruction Cycle Time: 8.1ns (2560fs, fs=48kHz)
Processing Step: 2560 steps (max) /fs= 48kHz, 44.1kHz (Normal Speed)
15360 steps (max) /fs= 8kHz, 7.35kHz
1280 steps (max) fs= 96kHz, 88.2kHz (Double Speed)
Multiplier: 24 x 16 40-bits (double precision available)
Divider: 24 ÷ 24 24-bits (floating point normalization function)
ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
24-bit arithmetic and logic operation
Data Shift: Right shift after multiplication 1, 2, 4, 5, 8, 14, 15-bits
Right shift BUS 1, 2, 3, 4, 8, 14, 15-bits
Left shift after multiplication 1, 2, 3, 4, 8, 15-bits
Left shift BUS 1, 2, 3, 4, 6, 8, 15-bits
Indirect shifting function
Program RAM (PRAM): 2048word x 36-bits
Coefficient RAM (CRAM): 2048word x 16-bits
Data RAM (DRAM): 2048word x 28-bits
Offset Register (OFREG): 64word x 13-bits
Delay RAM (DLRAM): 168kbit (four types)
6kword 28-bits
4kword 28-bits + 4kword 14-bits
3kword 28-bits + 6kword 14-bits
3kword 28-bits + 3kword 28-bits (Linear)
Register: 44-bits x 4 (ACC) [for ALU]
28-bits x 12 (TMP) [DBUS connection]
28-bits x 6 steps stack (PTMP) [DBUS connection]
MS1337-E-00-PB
- 1-
2011/11


AK7782 Datasheet
Recommendation AK7782 Datasheet
Part AK7782
Description Dual Audio DSP
Feature AK7782; [AK7782] AK7782 Dual Audio DSP with 24bit 5ch ADC & SRC GENERAL DESCRIPTION The AK7782 is an audio d.
Manufacture AKM
Datasheet
Download AK7782 Datasheet




AKM AK7782
[Stereo ADC, Common for ADC1 and ADC2]
24-bit 2ch x 2
S/(N+D): 90dB (fs=48kHz)
D-range: 96dBA (fs=48kHz)
S/N: 96dBA (fs=48kHz)
8ch bidirectional analog input selector
High-pass filter (HPF) for DC offset cancellation
fs=7.35kHz ~ 96kHz
[Mono ADC]
24bit 1ch
S/(N+D) 88dB (fs=48kHz)
D-range 95dBA (fs=48kHz)
S/N 95dBA (fs=48kHz)
High-pass filter (HPF) for DC offset cancellation
fs=7.35kHz ~ 96kHz
Digital volume control
[DSP1/DSP2 In/Output Digital Interface]
Serial Data Input: 14ch (including ADC block)
Serial Data Output: 16ch (each DSP outputs are 14ch)
Microcomputer Interface: 1ch In/Out or I2C-bus
[SRC, Common for SRC1 and SRC2]
2ch x 2
fs=7.35kHz ~ 96kHz
[General]
PLL
3.3V±0.3V, 1.8V ±0.1V
Operational Temperature: -40°C ~ 85°C
100pin LQFP
[AK7782]
MS1337-E-00-PB
- 2-
2011/11



AKM AK7782
Block Diagram
[AK7782]
4 2222222
ADC1
ADC2
ADCM
VOL
MUX
SDIN7/JX2
SDIN6 / JX1
SDIN5
JX2
JX1
P1IN6SEL
P1IN5SEL
SDIN4(32bit)
SDIN3(32bit)
SDIN2(32bit)
SDIN1
P1IN1SEL
PSRCSMUTE
PSRCRSTN
RSRC1SMUTE
RSRC1RSTN
SRCLRCK
SRCBICK
SRC2LRCK
SRC2BICK
NC
SRC1I SRC1O
SRC1LRCKO
SRC1BICKO
SRC1
SRC1LRCKI
SRC1BICKI
SRC1UNLOCK
0 P1IN7SEL
1
2 P1SDIN7
3
P1SDOUT7
0
1 P1SDIN6 P1SDOUT6
2
3
0
1 P1SDIN5 P1SDOUT5
2
3 IRPT1
P1SDIN4
P1SDOUT4
GPO11
P1SDIN3
P1SDOUT3
GPO10
P1SDIN2 P1SDOUT2
0
1
2 P1SDIN1 P1SDOUT1
3
DSP1
JX12
JX11
JX10
WDT1
P2IN7SEL
0 1 2 3 MSEL
0
1 P2SDIN7
2
3
P2IN6SEL
0
1
2 P2SDIN6
3
P2SDOUT7
P2SDOUT6
P2IN5SEL
0
1
2
3
P2SDIN5
P2SDOUT5
IRPT2
0
1
P2IN4SEL
0
1
P2IN3SEL
0
1
P2IN2SEL
P2SDIN4 P2SDOUT4
GPO21
P2SDIN3
P2SDIN2
P2SDOUT3
GPO20
P2SDOUT2
JX12E
JX11E
JX10E
0
1
2
3
P2IN1SEL
P2SDIN1
P2SDOUT1
JX22
JX21
JX20
DSP2
WDT2
LRCLKO
BITCLKO
TESTI2
TESTI1
CKM[2:0] 3
XTI
XTO
PCKRSTN
RCKRSTN
PDSPRSTN
PADRSTN
RDSPRSTN
RADRSTN
INITRSTN
CKRSTN
DSPRSTN
SRESETN
ADRSTN
RSRC2SMUTE
SRC2ISEL
0
1
2
3
SRC2I SRC2O
SRC2LRCKO
SRC2BICKO
RSRCRST2N
SRC2
0
1
2
SRC2CKI
0
1
2
SRC2LRCKI
SRC2BICKI
SRC2UNLOCK
0
1
2
SRC2CKO
0
1
2
CONTROLLER
(Master="H",Slave="L")
SMODE
pull down
Hi-z
I/O
ctrl reg sw
VREF
OUTASEL1
0
1
2
3
0
1
2
3
OUTASEL2
0
1
2
3 OUTAEN
OUT7SEL
0
1
2
3 OUT7EN
OUT6SEL
OUT6EN
2 VSS2
7 DVDD18
38 VSS3
63 DVDD
3 AVDD
3 VREFH
VCOM
VREFL
3 VSS1
SDOUTA
SDOUT7
SDOUT6
OUT5SEL1
0
1
2
3 OUT5EN
OUT4SEL
0
1
2
3 OUT4EN
0 OUT3SEL
1
2
3 OUT3EN
OUT2SEL
0
1
2
3 OUT2EN
0 OUT1SEL1
1
2
3 OUT1EN
JX22E
JX21E
JX20E
JX2
JX1
WDT1EN
CRCE
WDT2EN
LOCK1E
LOCK2E
SDOUT5
SDOUT4(32bit)
SDOUT3(32bit)
SDOUT2(32bit)
SDOUT1
JX0
STO
TESTO
CRC
MICIF
SI/CAD0
RQN/CAD1
SCLK/SCL
I2CSEL
SO
SDA
RDY
Figure 1. Block Diagram
MS1337-E-00-PB
- 3-
2011/11







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