Rx Mixer. ADRF6620 Datasheet

ADRF6620 Mixer. Datasheet pdf. Equivalent

ADRF6620 Datasheet
Recommendation ADRF6620 Datasheet
Part ADRF6620
Description 700 MHz to 2700 MHz Rx Mixer
Feature ADRF6620; Data Sheet 700 MHz to 2700 MHz Rx Mixer with Integrated IF DGA, Fractional-N PLL, and VCO ADRF6620 .
Manufacture Analog Devices
Datasheet
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Analog Devices ADRF6620
Data Sheet
700 MHz to 2700 MHz Rx Mixer with Integrated
IF DGA, Fractional-N PLL, and VCO
ADRF6620
FEATURES
Integrated fractional-N phase-locked loop (PLL)
RF input frequency range: 700 MHz to 2700 MHz
Internal local oscillator (LO) frequency range: 350 MHz to
2850 MHz
Input P1dB: 17 dBm
Output IP3: 45 dBm
Single-pole four-throw (SP4T) RF input switch
Digital step attenuator (DSA) range: 0 dB to 15 dB
Integrated RF tunable balun allowing single-ended 50 Ω input
Multicore integrated voltage controlled oscillator (VCO)
Digitally programmable variable gain amplifier (DGA)
−3 dB bandwidth: >600 MHz
Balanced 150 Ω IF output impedance
Programmable via 3-wire serial port interface (SPI)
Single 5 V supply
APPLICATIONS
Wireless receivers
Digital predistortion (DPD) receivers
GENERAL DESCRIPTION
The ADRF6620 is a highly integrated active mixer and synthesizer
that is ideally suited for wireless receiver subsystems. The feature
rich device consists of a high linearity broadband active mixer;
an integrated fractional-N PLL; low phase noise, multicore VCO;
and IF DGA. In addition, the ADRF6620 integrates a 4:1 RF
switch, an on-chip tunable RF balun, programmable RF attenuator,
and low dropout (LDO) regulators. This highly integrated device
fits within a small 7 mm × 7 mm footprint.
The high isolation 4:1 RF switch and on-chip tunable RF balun
enable the ADRF6620 to support four single-ended 50 Ω
terminated RF inputs. A programmable attenuator ensures
optimal RF input drive to the high linearity mixer core. The
integrated DSA has an attenuation range of 0 dB to 15 dB with
a step size of 1 dB.
FUNCTIONAL BLOCK DIAGRAM
RFIN0
RFIN1
RFIN2
RFIN3
IFOUT1–
IFOUT1+
IFOUT2–
IFOUT2+
REFIN
÷8
÷4
÷2
×1
×2
LOIN+
LOIN–
PFD CHARGE CP
+ PUMP
VTUNE
÷1, ÷2,
÷4, ÷8
N = INT + FRAC
MOD
÷2
LOIN+
LOIN–
VTUNE
CP
MUXOUT
LOCK_DET
VPTAT
LDO
2.5 V
SERIAL
PORT
INTERFACE
LDO
VCO
LDO
3.3V
Figure 1.
The ADRF6620 offers two alternatives for generating the dif-
ferential LO input signal: externally, via a high frequency, low
phase noise LO signal, or internally, via the on-chip fractional-N
PLL synthesizer. The integrated synthesizer enables continuous
LO coverage from 350 MHz to 2850 MHz. The PLL reference
input can support a wide frequency range because the divide and
multiply blocks can be used to increase or decrease the reference
frequency to the desired value before it is passed to the phase
frequency detector (PFD).
The integrated high linearity DGA provides an additional gain
range from 3 dB to 15 dB in steps of 0.5 dB for maximum flexibility
in driving an analog-to-digital converter (ADC).
The ADRF6620 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 48-lead, RoHS-compliant,
7 mm × 7 mm LFCSP package with an exposed pad. Performance
is specified over the −40°C to +85°C temperature range.
Rev. 0
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ADRF6620* PRODUCT PAGE QUICK LINKS
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COMPARABLE PARTS
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EVALUATION KITS
ADRF6620 Evaluation Board
DOCUMENTATION
Data Sheet
ADRF6620: 700 MHz to 2700 MHz Rx Mixer with
Integrated IF DGA, Fractional-N PLL, and VCO Data Sheet
User Guides
UG-558: Evaluating the ADRF6620, a 700 MHz to 2700
MHz Rx Mixer with Integrated IF Amplifier, Fractional-N
PLL, and VCO
SOFTWARE AND SYSTEMS REQUIREMENTS
ADRF6620 Evaluation Board Software
TOOLS AND SIMULATIONS
ADRF6620 S-Parameters
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
DESIGN RESOURCES
ADRF6620 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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Analog Devices ADRF6620
ADRF6620
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
RF Input to IF DGA Output System Specifications................. 3
Synthesizer/PLL Specifications................................................... 4
RF Input to Mixer Output Specifications.................................. 6
IF DGA Specifications ................................................................. 7
Digital Logic Specifications......................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
RF Input to DGA Output System Performance ..................... 11
Phase-Locked Loop (PLL)......................................................... 13
RF Input to Mixer Output Performance ................................. 17
IF DGA ........................................................................................ 20
Spurious Performance................................................................ 22
Theory of Operation ...................................................................... 24
RF Input Switches....................................................................... 24
Tunable Balun ............................................................................. 25
RF Digital Step Attenuator (DSA)............................................ 25
Active Mixer................................................................................ 25
Digitally Programmable Variable Gain Amplifier (DGA).... 25
LO Generation Block ................................................................. 26
REVISION HISTORY
7/13—Revision 0: Initial Version
Data Sheet
Serial Port Interface (SPI) ......................................................... 27
Basic Connections...................................................................... 28
RF Input Balun Insertion Loss Optimization......................... 30
IP3 and Noise Figure Optimization......................................... 31
Interstage Filtering Requirements............................................ 35
IF DGA vs. Load......................................................................... 38
ADC Interfacing ......................................................................... 39
Power Modes............................................................................... 40
Layout .......................................................................................... 40
Register Map ................................................................................... 41
Register Address Descriptions...................................................... 42
Register 0x00, Reset: 0x00000, Name: SOFT_RESET ........... 42
Register 0x01, Reset: 0x8B7F, Name: Enables ........................ 42
Register 0x02, Reset: 0x0058, Name: INT_DIV..................... 43
Register 0x03, Reset: 0x0250, Name: FRAC_DIV ................. 43
Register 0x04, Reset: 0x0600, Name: MOD_DIV.................. 43
Register 0x20, Reset: 0x0C26, Name: CP_CTL...................... 44
Register 0x21, Reset: 0x0003, Name: PFD_CTL .................... 45
Register 0x22, Reset: 0x000A, Name: FLO_CTL ................... 46
Register 0x23, Reset: 0x0000, Name: DGA_CTL................... 47
Register 0x30, Reset: 0x00000, Name: BALUN_CTL............ 48
Register 0x31, Reset: 0x08EF, Name: MIXER_CTL .............. 48
Register 0x40, Reset: 0x0010, Name: PFD_CTL2.................. 49
Register 0x42, Reset: 0x000E, Name: DITH_CTL1............... 50
Register 0x43, Reset: 0x0001, Name: DITH_CTL2 ............... 50
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 51
Rev. 0 | Page 2 of 52







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