FRACTIONAL-N PLL. HMC835LP6GE Datasheet

HMC835LP6GE PLL. Datasheet pdf. Equivalent

HMC835LP6GE Datasheet
Recommendation HMC835LP6GE Datasheet
Part HMC835LP6GE
Description FRACTIONAL-N PLL
Feature HMC835LP6GE; PLLs WITH INTEGRATED VCO - SMT HMC835LP6GE v04.1113 FRACTIONAL-N PLL WITH INTEGRATED VCO 33 - 4100 .
Manufacture Analog Devices
Datasheet
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Analog Devices HMC835LP6GE
HMC835LP6GE
v04.1113
FRACTIONAL-N PLL WITH INTEGRATED VCO
33 - 4100 MHz
Features
Wideband: 33 - 4100 MHz
Maximum Phase Detector Rate: 100 MHz
Low Phase Noise: -110 dBc/Hz in Band @2GHz
PLL FOM:
-230 dBc/Hz Integer Mode, -227 dBc/Hz Fractional
Mode
< 94 fs Integrated RMS Jitter (1 kHz to 100 MHz)
Low Noise Floor: -167 dBc/Hz
2 Differential RF outputs
Typical Applications
MIMO Radio Architectures
Cellular Infrastructure
Cellular backhaul
Communication Test Equipment
CATV Equipment
Functional Diagram
External LO Input
Exact Frequency Mode:
0 Hz Fractional Frequency Error
Programmable RF Output Phase
Output Phase Synchronous Frequency Changes
Output Phase Synchronization
RF Output Mute Function
40 Lead 6x6 mm SMT Package: 36 mm2
Phased Array Applications
DDS Replacement
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Analog Devices HMC835LP6GE
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Analog Devices HMC835LP6GE
HMC835LP6GE
v04.1113
FRACTIONAL-N PLL WITH INTEGRATED VCO
33 - 4100 MHz
General Description
The HMC835LP6GE is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental
frequency of 2050 to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable
the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a delta-
sigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along
with excellent spectral performance.
Two independent RF outputs, with independent gain control, enable the HMC835LP6GE to distribute identical
frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output.
An external VCO input allows the HMC835LP6GE to lock external VCOs, and enables cascaded LO architectures for
MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both
integrated and external VCOs, and seamless switching between integrated or external VCOs during operation.
Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling
scalable MIMO and beam-forming radio architectures.
Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact
Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error, and
the ability to synchronously change frequencies without changing the phase of the output signal.
Electrical Specifications
VPPCP, VDDLS, VCC1, VCC2 = 5 V; RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V Min and Max Specified
across Temp -40 °C to 85 °C
Parameter
RF Output Characteristics
Condition
Min.
Typ.
Max.
Units
Output Frequency
33
4100
MHz
VCO Frequency at PLL Input
2050
4100
MHz
RF Output Frequency at fVCO
Output Power
2050
4100
MHz
RF Output Power at fundmental frequency at
2050 MHz
Max Gain Setting
Reg 16h[7:6]=11
Differential (100 Ohm load).
Output power varies with
frequency and output configu-
ration.
See Figures 11, 12, 13, 14
5
dBm
Output Power Control range
3 dB Steps
9 dB
Harmonics for Fundamental Mode
fo Mode at 2 GHz
2nd / 3rd / 4th
-26/-20/-39
dBc
fo/2 Mode at 2GHz/2 = 1 GHz
2nd / 3rd / 4th
-27/-17/-35
dBc
fo/30 Mode at 3 GHz/30 = 100 MHz
2nd / 3rd / 4th
-26/-10/-38
dBc
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