Clock Generator. AD9518-2 Datasheet

AD9518-2 Generator. Datasheet pdf. Equivalent

AD9518-2 Datasheet
Recommendation AD9518-2 Datasheet
Part AD9518-2
Description 6-Output Clock Generator
Feature AD9518-2; Data Sheet FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.05 GHz to 2.33.
Manufacture Analog Devices
Datasheet
Download AD9518-2 Datasheet




Analog Devices AD9518-2
Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.05 GHz to 2.33 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9518-21 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz
to 2.33 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9518-2 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
The AD9518-2 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
For applications that require additional outputs, a crystal
reference input, zero-delay, or EEPROM for automatic
configuration at startup, the AD9520 and AD9522 are available.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
6-Output Clock Generator with
Integrated 2.2 GHz VCO
AD9518-2
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
LVPECL
LVPECL
LVPECL
AD9518-2
Figure 1.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
In addition, the AD9516 and AD9517 are similar to the AD9518
but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32.
The AD9518-2 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-2 is specified for operation over the industrial
range of −40°C to +85°C.
1 AD9518 is used throughout the data sheet to refer to all the members of the
AD9518 family. However, when AD9518-2 is used, it refers to that specific
member of the AD9518 family.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.



Analog Devices AD9518-2
AD9518-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 6
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 7
Clock Output Absolute Phase Noise (Internal VCO Used).... 7
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO).................................................................... 8
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO)............................................................................... 8
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) ................................................................ 8
Clock Output Additive Time Jitter (VCO Divider
Not Used)....................................................................................... 9
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Serial Control Port ..................................................................... 10
PD, SYNC, and RESET Pins ..................................................... 10
LD, STATUS, and REFMON Pins............................................ 11
Power Dissipation....................................................................... 11
Timing Diagrams............................................................................ 12
Absolute Maximum Ratings.......................................................... 13
Data Sheet
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 20
Detailed Block Diagram ................................................................ 21
Theory of Operation ...................................................................... 22
Operational Configurations...................................................... 22
Digital Lock Detect (DLD) ....................................................... 30
Clock Distribution ..................................................................... 34
Reset Modes ................................................................................ 38
Power-Down Modes .................................................................. 38
Serial Control Port ......................................................................... 40
Serial Control Port Pin Descriptions ....................................... 40
General Operation of Serial Control Port............................... 40
The Instruction Word (16 Bits) ................................................ 41
MSB/LSB First Transfers ........................................................... 41
Thermal Performance.................................................................... 44
Control Registers ............................................................................ 45
Control Register Map Overview .............................................. 45
Control Register Map Descriptions ......................................... 47
Applications Information .............................................................. 59
Frequency Planning Using the AD9518.................................. 59
Using the AD9518 Outputs for ADC Clock Applications.... 59
LVPECL Clock Distribution ..................................................... 60
Outline Dimensions ....................................................................... 61
Ordering Guide .......................................................................... 61
Rev. C | Page 2 of 64



Analog Devices AD9518-2
Data Sheet
REVISION HISTORY
1/12—Rev. B to Rev.C
Change to 0x232 Description, Table 49........................................58
9/11—Rev. A to Rev. B
Changes to Applications and General Description Sections.......1
Change to CPRSET Pin Resistor Parameter, Table 1....................4
Changes to Table 2 ............................................................................4
Change to Test Conditions/Comments Column of Output
Differential Voltage (VOD) Parameter, Table 4 ...............................5
Change to Logic 1 Current and Logic 0 Current Parameters,
Table 14.............................................................................................10
Change to Test Conditions/Comments Column of LVPECL
Channel (Divider Plus Output Driver) Parameter, Table 16 .....11
Changes to Table 19 ........................................................................14
Changes to Captions, Figure 11 and Figure 16............................17
Added Figure 26, Renumbered Sequentially ...............................19
Change to PLL External Loop Filter Section...............................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to Comments/Conditions Column, Table 27 ..............29
Changes to Automatic/Internal Holdover Mode and
Frequency Status Monitors Sections.............................................32
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Write Section.................................................................40
Change to Figure 47 ........................................................................42
Changes to Table 41 ........................................................................44
Changes to Register Address 0x01C, Table 42 ............................45
Changes to Register Address 0x017, Bits[1:0] and
Register Address 0x018, Bits[2:0], Table 44 .................................50
Changes to Register Address 0x01C, Bits[5:1], Table 44............53
Change to Bit 5, Register Address 0x191, Register
Address 0x194, and Register Address 0x197, Table 46...............56
Changes to LVPECL Clock Distribution Section .......................60
Updated Outline Dimensions and Changes to
Ordering Guide ...............................................................................61
1/10—Rev. 0 to Rev. A
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal
AD9518-2
Changes to Features, Applications, and General Description.....1
Change to CPRSET Pin Resistor Parameter..................................4
Changes to VCP Supply Parameter.................................................11
Changes to Table 18 ........................................................................13
Added Exposed Paddle Notation to Figure 4;
Changes to Table 19 ........................................................................14
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 21..........22
Changes to Table 23 ........................................................................24
Change to Configuration and Register Settings Section ...........25
Change to Phase Frequency Detector (PFD) Section ................26
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........27
Change to Figure 31; Added Figure 32.........................................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to A and B Counters Section and Table 27 ..................29
Change to Holdover Section..........................................................31
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Table 32; Change to Channel Frequency
Division (0, 1, and 2) Section ........................................................35
Change to Write Section ................................................................40
Change to Figure 46........................................................................42
Added Thermal Performance Section; Added Table 41 ............44
Changes to 0x003 Register Address..............................................45
Changes to Table 43 ........................................................................47
Changes to Table 44 ........................................................................48
Changes to Table 45 ........................................................................55
Changes to Table 46 ........................................................................57
Changes to Table 47 ........................................................................58
Changes to Table 48 ........................................................................59
Added Frequency Planning Using the AD9518 Section............60
Changes to LVDS Clock Distribution Section ............................61
Changes to Figure 52 and Figure 54; Added Figure 53..............61
Added Exposed Paddle Notation to Outline Dimensions;
Changes to Ordering Guide...........................................................62
9/07—Revision 0: Initial Version
Rev. C | Page 3 of 64







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