Frequency Synthesizer. ADF4196 Datasheet

ADF4196 Synthesizer. Datasheet pdf. Equivalent

ADF4196 Datasheet
Recommendation ADF4196 Datasheet
Part ADF4196
Description 6 GHz PLL Frequency Synthesizer
Feature ADF4196; Data Sheet Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 FEATURES Fast s.
Manufacture Analog Devices
Datasheet
Download ADF4196 Datasheet




Analog Devices ADF4196
Data Sheet
Low Phase Noise, Fast Settling, 6 GHz
PLL Frequency Synthesizer
ADF4196
FEATURES
Fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
within 20 μs
1 degree rms phase error at 4 GHz RF output
Digitally programmable output phase
RF input range up to 6 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Pulse Doppler radar
Instrumentation and test equipment
Beam-forming/phased array systems
GENERAL DESCRIPTION
The ADF4196 frequency synthesizer can be used to implement
local oscillators (LO) in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time require-
ments for base stations, and the fast settling feature makes the
ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency
detector (PFD) and a precision differential charge pump.
A differential amplifier converts the differential charge pump
output to a single-ended voltage for the external voltage controlled
oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter-
polator, working with the N divider, allows programmable modulus
fractional-N division. Additionally, the 4-bit reference (R) counter
and on-chip frequency doubler allow selectable reference signal
(REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a VCO. The
switching architecture ensures that the PLL settles within the
GSM time slot guard period, removing the need for a second
PLL and associated isolation switches. This decreases the cost,
complexity, PCB area, shielding, and characterization found on
previous ping-pong GSM PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
SDVDD DVDD1 DVDD2 DVDD3 AVDD
VP1 VP2 VP3
RSET
REFIN
MUXOUT
CLK
DATA
LE
×2
DOUBLER
HIGH-Z
OUTPUT
MUX
24-BIT
DATA
REGISTER
4-BIT R
COUNTER
/2
DIVIDER
VDD
DGND
LOCK DETECT
RDIV
NDIV
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE +
PUMP
DIFFERENTIAL
AMPLIFIER
+
N COUNTER
FRACTION MODULUS
REG
REG
INTEGER
REG
ADF4196
SW1
CPOUT+
CPOUT–
SW2
CMR
AIN–
AIN+
AOUT
SW3
RFIN+
RFIN–
AGND1
AGND2
DGND1
DGND2
Figure 1.
DGND3 SDGND SWGND
Rev. D
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Analog Devices ADF4196
ADF4196* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
ADF4196 Evaluation Board
DOCUMENTATION
Application Notes
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
ADF4196: Low Phase Noise, Fast Settling, 6 GHz PLL
Frequency Synthesizer Data Sheet
User Guides
UG-476: PLL Software Installation Guide
UG-536: Evaluating the ADF4193 and ADF4196 Frequency
Synthesizers for Phase-Locked Loops
TOOLS AND SIMULATIONS
• ADIsimPLL™
ADIsimRF
REFERENCE MATERIALS
Press
• New Analog Devices’ PLL Synthesizers Deliver Utmost
Flexibility and Phase Noise Performance
Product Selection Guide
RF Source Booklet
DESIGN RESOURCES
ADF4196 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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Analog Devices ADF4196
ADF4196
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Transistor Count........................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
General Description................................................................... 11
Reference Input........................................................................... 11
RF Input Stage............................................................................. 11
PFD and Charge Pump.............................................................. 12
Differential Charge Pump ......................................................... 12
Fast Lock Timeout Counters..................................................... 12
Differential Amplifier ................................................................ 13
MUXOUT and Lock Detect ......................................................... 13
REVISION HISTORY
5/15—Rev. C to Rev. D
Changed LFCSP_VQ to LFCSP_WQ ......................... Throughout
Changes to Figure 3.......................................................................... 6
Changed ADuC70xx Interface Section to Analog
Microcontroller Interface Section ................................................ 27
Changes to Analog Microcontroller Interface Section and
Figure 38 .......................................................................................... 27
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
1/13—Rev. B to Rev. C
Change to Power-Up Initialization Section ................................ 23
Changes to Ordering Guide .......................................................... 28
12/11—Rev. A to Rev. B
Changes to Figure 10, Figure 11, Figure 13, and
Figure 14 ............................................................................................ 9
Change to Figure 31 ....................................................................... 17
10/11—Revision A: Initial Version
Data Sheet
Input Shift Register .................................................................... 13
Register Map ................................................................................... 14
FRAC/INT Register (R0) Latch Map....................................... 15
MOD/R Register (R1) Latch Map ............................................ 16
Phase Register (R2) Bit Latch Map .......................................... 17
Function Register (R3) Latch Map........................................... 18
Charge Pump Register (R4) Latch Map .................................. 19
Power-Down Register (R5) Bit Map ........................................ 20
Mux Register (R6) Latch Map and Truth Table ..................... 21
Programming the ADF4196.......................................................... 22
Worked Example ........................................................................ 22
Spur Mechanisms ....................................................................... 22
Power-Up Initialization ............................................................. 23
Changing the Frequency of the PLL and the Phase Lookup
Table ............................................................................................. 23
Applications Information .............................................................. 25
Local Oscillator for a GSM Base Station ................................. 25
Interfacing ................................................................................... 27
PCB Design Guidelines ............................................................. 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. D | Page 2 of 28







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