Clock Generator. CY24271 Datasheet

CY24271 Generator. Datasheet pdf. Equivalent

CY24271 Datasheet
Recommendation CY24271 Datasheet
Part CY24271
Description Clock Generator
Feature CY24271; CY24271 Rambus® XDR™ Clock Generator Rambus® XDR™ Clock Generator Features ■ Meets Rambus Extended.
Manufacture Cypress Semiconductor
Datasheet
Download CY24271 Datasheet




Cypress Semiconductor CY24271
CY24271
Rambus® XDR™ Clock Generator
Rambus® XDR™ Clock Generator
Features
Meets RambusExtended Data Rate (XDR™) clocking
requirements
25 ps typical cycle-to-cycle jitter
135 dBc/Hz typical phase noise at 20 MHz offset
100 or 133 MHz differential clock input
300–800 MHz high speed clock support
Quad (open drain) differential output drivers
Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
Spread Aware™
2.5 V operation
28-pin TSSOP package
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
/B YPA SS
EN
Bypass
MUX
REFCLK,REFC LKB
PLL
EN
RegA
EN
RegB
EN
RegC
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
SDA ID0 ID1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00411 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 20, 2016



Cypress Semiconductor CY24271
CY24271
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
PLL Multiplier ............................................................... 4
Device ID and SMBus Device Address ....................... 4
Modes of Operation ..................................................... 5
SMBus Protocol ........................................................... 6
Input Clock Signal ....................................................... 6
SMBus Data Byte Definitions ...................................... 6
Absolute Maximum Conditions ....................................... 8
DC Operating Conditions ................................................. 8
DC Electrical Specifications ............................................ 9
Thermal Resistance .......................................................... 9
AC Operating Conditions ............................................... 10
AC Electrical Specifications .......................................... 11
Test and Measurement Setup ........................................ 12
Signal Waveforms .......................................................... 13
Jitter ................................................................................. 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimension ................................. 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 001-00411 Rev. *F
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Cypress Semiconductor CY24271
Pinouts
Figure 1. 28-pin TSSOP pinout
VDDP
VSSP
ISET
VSS
REFCLK
REFCLKB
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
/BYPASS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 CLK0
26 CLK0B
25 VSS
24 CLK1
23 CLK1B
22 VDD
21 VSS
20 CLK2
19 CLK2B
18 VSS
17 CLK3
16 CLK3B
15 VDD
Pin Definitions
28-pin TSSOP
Pin No. Name
1 VDDP
2 VSSP
3 ISET
4 VSS
5 REFCLK
6 REFCLKB
7 VDDC
8 VSSC
9 SCL
10 SDA
11 EN
12 ID0
13 ID1
14 /BYPASS
15 VDD
16 CLK3B
17 CLK3
18 VSS
19 CLK2B
20 CLK2
21 VSS
22 VDD
23 CLK1B
24 CLK1
25 VSS
I/O
PWR
GND
I
GND
I
I
PWR
GND
I
I
I
I
I
I
PWR
O
O
GND
O
O
GND
PWR
O
O
GND
Description
2.5 V power supply for phased lock loop (PLL)
Ground
Set clock driver current (external resistor)
Ground
Reference clock input (connect to clock source)
Complement of reference clock (connect to clock source)
2.5 V power supply for core
Ground
SMBus clock (connect to smbus)
SMBus data (connect to smbus)
Output Enable (CMOS signal)
Device ID (CMOS signal)
Device ID (CMOS signal)
REFCLK bypassing PLL (CMOS signal)
Power supply for outputs
Complement clock output
Clock output
Ground
Complement clock output
Clock output
Ground
Power supply for outputs
Complement clock output
Clock output
Ground
Document Number: 001-00411 Rev. *F
CY24271
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