GaAs MMIC. NJG1665MD7 Datasheet

NJG1665MD7 MMIC. Datasheet pdf. Equivalent

NJG1665MD7 Datasheet
Recommendation NJG1665MD7 Datasheet
Part NJG1665MD7
Description SP5T SWITCH GaAs MMIC
Feature NJG1665MD7; NJG1665MD7 SP5T SWITCH GaAs MMIC I GENERAL DESCRIPTION The NJG1665MD7 is a GaAS SP5T switch featur.
Manufacture New Japan Radio
Datasheet
Download NJG1665MD7 Datasheet




New Japan Radio NJG1665MD7
NJG1665MD7
SP5T SWITCH GaAs MMIC
I GENERAL DESCRIPTION
The NJG1665MD7 is a GaAS SP5T switch featured low insertion loss,
high isolation and small size package, and suited for mobile terminal
applications. The NJG1665MD7 switches a path between common RF
port and five RF ports by three bit control signal from 1.3V of logical high
voltage. In addition, this switch includes ESD protection circuits for good
ESD tolerance. The NJG1665MD7 is available in a very small, lead-free,
halogen-free, 1.6mm x 1.6mm x 0.397 mm, 14-pin EQFN14-D7 package.
I PACKAGE OUTLINE
NJG1665MD7
I APPLICATIONS
Multi-mode LTE, UMTS, CDMA and GSM applications
Receive system, RX path, and Diversity antenna applications
Mobile phone, Tablet PC, Data card, Modem and Router applications
I FEATURES
G Low control voltage
G Low operating voltage
G Low insertion loss
G High ESD tolerance
G Small and thin package
G Lead -free and halogen-free
VCTL(H)=+1.3V min
VDD =+2.0~+4.5V
0.40 dB typ. @f=1.0GHz, PIN=23dBm
0.50 dB typ. @f=2.0GHz, PIN=23dBm
0.60 dB typ. @f=2.5GHz, PIN=23dBm
On-chip ESD protection circuit
EQFN14-D7 (package size: 1.6mm x 1.6mm x 0.397mm typ.)
I PIN CONFIGURATION
(Top view)
14 13 12
1 11
DECODER
2 10
39
I TRUTH TABLE
48
567
Pin connection
1. GND
2. VDD
3. P5
4. GND
5. P4
6. P3
7. P2
8. GND
9. P1
10. PC
11. GND
12. CTL3
13. CTL2
14. CTL1
PATH
CTL1 CTL2 CTL3
PC-P1
L
H
L
PC-P2
H
H
L
PC-P3
L
H
H
PC-P4
H
H
H
PC-P5
X
L
L
"H"…VCTL(H), "L"…VCTL(L) , “X” …Do not care.
NOTE: The information on this datasheet is subject to change without notice
Ver. 2013-05-02
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New Japan Radio NJG1665MD7
NJG1665MD7
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RF input power
Supply voltage
Control voltage
Power dissipation
Operating temp.
Storage temp.
SYMBOL
CONDITIONS
PIN VDD =2.7V, VCTL=0V / 1.8 V
VDD VDD terminal
VCTL CTL1~3 terminals
PD
Four-layer FR4 PCB with through-hole
(74.2mmx74.2mm), Tj=150°C
Topr
Tstg
(Ta=+25°C, Zs=Zl=50)
RATINGS UNITS
30 dBm
5.0 V
5.0 V
1300
mW
-40~+85
-55~+150
°C
°C
ELECTRICAL CHARACTERISTICS (DC)
(General conditions: VDD=2.7 V, VCTL(L)=0 V, VCTL(H)=1.8 V, Zs=Zl=50 , Ta=+25°C, with application circuit)
PARAMETERS SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Supply voltage
VDD
2.0 2.7 4.5
V
Operating current
Control voltage
(LOW)
Control voltage
(HIGH)
Control Current
IDD f=2.0GHz, PIN=23 dBm
VCTL(L)
VCTL(H)
ICTL
45 100 µA
0 - 0.4 V
1.3 1.8 4.5
V
- 5 10 µA
ELECTRICAL CHARACTERISTICS (RF)
(General conditions: VDD=2.7 V, VCTL(L)=0 V, VCTL(H)=1.8 V, Zs=Zl=50 , Ta=+25°C, with application circuit)
PARAMETERS SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Insertion Loss1
LOSS1 f=1.0 GHz, PIN =23 dBm
-
0.40 0.60
dB
Insertion Loss2
LOSS2 f=2.0 GHz, PIN =23 dBm
-
0.50 0.70
dB
Insertion Loss3
LOSS3 f=2.5 GHz, PIN =23 dBm
-
0.60 0.80
dB
Isolation1
ISL1 f=1.0 GHz, PIN =23 dBm
25 29 - dB
Isolation2
ISL2 f=2.0 GHz, PIN =23 dBm
Isolation3
Input Power at 0.2dB
Compression Point
ISL3
P-0.2dB
f=2.5 GHz, PIN =23 dBm
f=2.0 GHz
VSWR
VSWR f=2.0 GHz, ON state
20 23 - dB
18 21 - dB
26 29
- dBm
1.2 1.5
Switching Time
TSW 50% CTL to 10%/90% RF
1 5 µs
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New Japan Radio NJG1665MD7
NJG1665MD7
I TERMINAL INFORMATION
No. SYMBOL
DESCRIPTION
1 GND Ground terminal. Connect to the PCB ground plane.
2
VDD
Power supply input. This terminal should be connected to GND via a bypass
capacitor.
3
P5
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
4 GND Ground terminal. Connect to the PCB ground plane.
5
P4
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
6
P3
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
7
P2
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
8 GND Ground terminal. Connect to the PCB ground plane.
9
P1
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
10
PC
Common RF input / output port. External capacitor is required to block the DC
bias voltage of internal circuit.
11 GND Ground terminal. Connect to the PCB ground plane.
12 CTL3 Control port. “High level” is DC +1.3V~4.5V, “Low level” is DC 0~+0.4V.
13 CTL2 Control port. “High level” is DC +1.3V~4.5V, “Low level” is DC 0~+0.4V.
14 CTL1 Control port. “High level” is DC +1.3V~4.5V, “Low level” is DC 0~+0.4V.
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