TDM Conversion. ADAU7002 Datasheet

ADAU7002 Conversion. Datasheet pdf. Equivalent

ADAU7002 Datasheet
Recommendation ADAU7002 Datasheet
Part ADAU7002
Description Stereo PDM-to-I2S or TDM Conversion
Feature ADAU7002; Data Sheet Stereo PDM-to-I2S or TDM Conversion IC ADAU7002 FEATURES 64× decimation of a stereo pul.
Manufacture Analog Devices
Datasheet
Download ADAU7002 Datasheet




Analog Devices ADAU7002
Data Sheet
Stereo PDM-to-I2S or
TDM Conversion IC
ADAU7002
FEATURES
64× decimation of a stereo pulse density modulation (PDM)
bit stream to pulse code modulation (PCM) audio data
Slave I2S or time division multiplexed (TDM) output interface
Configurable TDM slots
I/O supply operation: 1.62 V to 3.6 V
64× output sample rate PDM clock
64×/128×/192×/256×/384×/512× output sample rate BCLK
Automatic BCLK ratio detection
Output sample rate: 4 kHz to 96 kHz
Automatic PDM CLK drive at 64× the sample rate
Automatic power down with BCLK removal
0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply
Shutdown current: <1 μA
8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP
Power-on reset
GENERAL DESCRIPTION
The ADAU7002 converts a stereo PDM bit stream into a PCM
output. The source for the PDM data can be two microphones
or other PDM sources. The PCM audio data is output on a
serial audio interface port in either I2S or TDM format.
The ADAU7002 is specified over the commercial temperature
range (−40°C to +85°C). It is available in a halide-free, 8-ball,
1.56 mm × 0.76 mm, wafer level chip scale package (WLCSP).
APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics
FUNCTIONAL BLOCK DIAGRAM
1.62V TO 3.6V
PDM_CLK
PDM_DAT
CONFIG GND
IOVDD
PDM
INPUT
PORT
DIGITAL
DECIMATION
FILTERING
I2S
OUTPUT
PORT
Figure 1.
ADAU7002
BCLK
LRCLK
SDATA
Rev. C
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Analog Devices ADAU7002
ADAU7002
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
REVISION HISTORY
11/2019—Rev. B to Rev. C
Changes to Figure 12........................................................................ 9
11/2016—Rev. A to Rev. B
Change to Serial Port Timing Section and Time From BCLK
Falling Parameter; Table 7 ............................................................. 10
Changes to Figure 19 Caption and Figure 21 Caption .............. 12
Data Sheet
Pin Configuration and Function Descriptions..............................5
Typical Performance Characteristics ..............................................6
Typical Application Circuit ..............................................................8
Applications Information .................................................................9
Overview ........................................................................................9
Clocking..........................................................................................9
Serial Audio Output Interface .....................................................9
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
7/2013—Rev. 0 to Rev. A
Changes to Supply Current Test Conditions/Comments ............3
Changes to Figure 5...........................................................................6
Added Figure 6; Renumbered Sequentially ...................................6
Changes to Figure 14 and Figure 15 ............................................ 10
Changes to Figure 16, Figure 17, and Figure 18 ......................... 11
Changes to Figure 19, Figure 20, and Figure 21 ......................... 12
1/2013—Revision 0: Initial Version
Rev. C | Page 2 of 16



Analog Devices ADAU7002
Data Sheet
ADAU7002
SPECIFICATIONS
IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted.
Table 1.
Parameter
DIGITAL INPUT/OUTPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage, High (IIH)
Input Leakage, Low (IIL)
Input Capacitance
SDATA
PDM_CLK
PERFORMANCE
Dynamic Range
With A-Weighted Filter (RMS)
Signal-to-Noise-Ratio
Decimation Ratio
Frequency Response
Stop Band
Stop-Band Attenuation
Group Delay
Gain
Start-Up Time
Bit Width
Interchannel Phase
CLOCKING
Output Sampling Rate
BCLK Frequency
POWER SUPPLIES
Supply Voltage Range
Supply Current
Shutdown Current
Test Conditions/Comments
BCLK and LRCLK pins
BCLK and LRCLK pins
20 Hz to 20 kHz, −60 dB input
A-weighted, fourth-order input
DC to 0.45 output fS
0.02 fS input signal
PDM to PCM
Internal and output
fS LRCLK pulse rate
fBCLK
IOVDD
IOVDD = 1.8 V
IOVDD = 3.3 V
IOVDD = 1.8 V, 16 kHz output
IOVDD = 3.3 V, 16 kHz output
IOVDDSD, no input clocks
Min Typ
0.7 × IOVDD
0.3 × IOVDD
4.5
9
110
110
64×
−0.1
0.566
60
3.31
0
48
20
0
4
0.256
48
3.072
1.62
0.67
1.33
0.21
0.41
1
Max
Unit
V
V
1
µA
1
µA
5
pF
mA
mA
dB
dB
+0.01
dB
fS
dB
LRCLK cycles
dB
LRCLK cycles
Bits
Degrees
96
kHz
24.576 MHz
3.6
V
mA
mA
mA
mA
µA
Rev. C | Page 3 of 16







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