Clock Buffer. CY7B9945V Datasheet

CY7B9945V Buffer. Datasheet pdf. Equivalent

CY7B9945V Datasheet
Recommendation CY7B9945V Datasheet
Part CY7B9945V
Description High-Speed Multi-Phase PLL Clock Buffer
Feature CY7B9945V; CY7B9945V RoboClock® High-Speed Multi-Phase PLL Clock Buffer High-Speed Multi-Phase PLL Clock Buffe.
Manufacture Cypress Semiconductor
Datasheet
Download CY7B9945V Datasheet




Cypress Semiconductor CY7B9945V
CY7B9945V RoboClock®
High-Speed Multi-Phase
PLL Clock Buffer
High-Speed Multi-Phase PLL Clock Buffer
Features
500 ps max Total Timing Budget (TTB™) window
24 MHz–200 MHz input and Output Operation
Low Output-output skew < 200 ps
10 + 1 LVTTL outputs driving 50 terminated lines
Dedicated feedback output
Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns
3.3-V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable
Reference Inputs
Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
Individual Output Bank Disable
Output High Impedance Option for Testing Purposes
Integrated Phase Locked Loop (PLL) with Lock Indicator
Low Cycle-cycle jitter (<100 ps peak-peak)
3.3 V Operation
Industrial Temperature Range: –40 °C to +85 °C
52-pin 1.4 mm TQFP package
Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks. This includes the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50 while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in
625 ps–1300 ps increments up to ±10.4 ns. The dedicated
feedback output enables divide-by functionality from 1 to 12 and
limited phase adjustments. However, if needed, any one of the
ten outputs can be connected to the feedback input as well as
driving other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation, click here.
Logic Block Diagram
FS
REFA+
REFA-
REFB+
REFB-
REFSEL
FBK
MODE
3
PLL
FBF0
FBDS0
FBDS1
1F0
1F1
1D S 0
1D S 1
1F2
1F3
3
3
3
3
3
3
3
3
3
2F0
2F1
2DS0
2D S 1
3
3
3
3
LO C K
D iv id e
and
Phase
S e le c t
D iv id e
and
Phase
S e le c t
D IS 1
D iv id e
and
Phase
S e le c t
D IS 2
QF
1Q 0
1Q 1
1Q 2
1Q 3
2Q 0
2Q 1
2Q 2
2Q 3
2Q 4
2Q 5
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07336 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 8, 2019



Cypress Semiconductor CY7B9945V
CY7B9945V RoboClock®
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Block Diagram Description .............................................. 5
Time Unit Definition ..................................................... 5
Divide and Phase Select Matrix .................................. 6
Output Disable Description .......................................... 8
Lock Detect Output Description ................................... 8
Factory Test Mode Description ................................... 8
Safe Operating Zone ................................................... 8
Absolute Maximum Conditions ....................................... 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
AC Timing Diagram ........................................................ 13
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagram ............................................................ 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-07336 Rev. *P
Page 2 of 19



Cypress Semiconductor CY7B9945V
Pinouts
CY7B9945V RoboClock®
Figure 1. 52-pin TQFP pinout
2F1
2F0
2DS1
GND
2Q0
VCCN
2Q1
2Q2
VCCN
2Q3
GND
1DS1
2DS0
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6
7
CY7B9945V
34
33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
REFA-
REFSEL
REFB-
REFB+
1F2
FS
GND
1Q2
VCCN
1Q3
FBF0
1F0
VCCQ
Document Number: 38-07336 Rev. *P
Page 3 of 19







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