Peripheral Controller. CYWB0125AB Datasheet

CYWB0125AB Controller. Datasheet pdf. Equivalent

CYWB0125AB Datasheet
Recommendation CYWB0125AB Datasheet
Part CYWB0125AB
Description USB/Mass Storage Peripheral Controller
Feature CYWB0125AB; ADVANCE INFORMATION CYWB012X Family West Bridge® Antioch™ West Bridge® Antioch™ Features ■ SLIM® a.
Manufacture Cypress Semiconductor
Datasheet
Download CYWB0125AB Datasheet




Cypress Semiconductor CYWB0125AB
CYWB0124AB
CYWB0125AB
West Bridge® Antioch™
USB/Mass Storage Peripheral Controller
West Bridge® Antioch™ USB/Mass Storage Peripheral Controller
Features
SLIMarchitecture, enabling simultaneous and independent
data paths between processor and USB, and between USB
and mass storage
High speed USB at 480 Mbps
USB-2.0 compliant
Integrated USB 2.0 transceiver, smart serial interface engine
16 programmable endpoints
Mass storage device support
MMC/MMC+/SD/CE-ATA
NAND flash: × 8 or × 16, SLC
Full NAND management (ECC, wear leveling)
Memory mapped interface to main processor
DMA slave support
Supports Microsoft® media transfer protocol (MTP) with
optimized data throughput
Ultra low power, 1.8 V core operation
Low power modes
Small footprint, 6 × 6 mm VFBGA, and less than 4 × 4 mm
WLCSP
Selectable clock input frequencies
19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
Applications
Cellular phones
Portable media players
Personal digital assistants
Digital cameras
Portable video recorder
Logic Block Diagram
West Bridge Antioch
Control 8051
Registers MCU
PU
SLIMTM
Mass Storage Interface
SD/MMC+/CE-ATA
NAND
S
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07978 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 1, 2017



Cypress Semiconductor CYWB0125AB
CYWB0124AB
CYWB0125AB
Contents
Functional Overview ........................................................ 3
SLIM™ Architecture .................................................... 3
Turbo-MTP Support ..................................................... 3
8051 Microprocessor ................................................... 3
Configuration and Status Registers ............................. 3
Processor Interface (P-port) ........................................ 3
USB Interface (U-Port) ................................................ 3
Mass Storage Support (S-Port) ................................... 3
Clocking ....................................................................... 4
Power Domains ........................................................... 5
Power Modes .............................................................. 5
Antioch in WLCSP ....................................................... 6
Absolute Maximum Ratings .......................................... 12
Operating Conditions ..................................................... 12
DC Characteristics ......................................................... 12
USB Transceiver ....................................................... 14
Capacitance .................................................................... 14
AC Test Loads and Waveforms ..................................... 14
AC Characteristics ......................................................... 15
USB Transceiver ....................................................... 15
P-Port Interface ......................................................... 15
SD/MMC Parameters ................................................ 22
Reset and Standby Timing Parameters .................... 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC®Solutions ....................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-07978 Rev. *O
Page 2 of 31



Cypress Semiconductor CYWB0125AB
CYWB0124AB
CYWB0125AB
Functional Overview
SLIMArchitecture
The Simultaneous Link to Independent Multimedia (SLIM)
architecture allows three different interfaces (the P-port, the
S-port, and the U-port) to connect to one another independently.
With this architecture, using Antioch™ to connect a device to a
PC through an USB does not disturb the functions of the device.
It still accesses mass storage at the same time the PC is
synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
PC accesses a mass storage device independent of the main
processor, or enumerates access to both the mass storage and
the main processor at the same time.
In a handset, this typically enables the user to use the phone as
a thumb drive or download media files to the phone while still
having full functionality available on the phone. The same phone
even functions as a modem to connect the PC to the web.
Turbo-MTP Support
Turbo-MTP is an implementation of Microsoft’s Media Transfer
Protocol (MTP) enabled by West Bridge® Antioch™. In the
current generation of MTP-enabled mobile phones, all protocol
packets need to be handled by the main processor. West Bridge
Turbo-MTP switches these packet types and sends only control
packets to the processor, while data payloads are written directly
to mass storage. This brings the high performance of West
Bridge to MTP. For more information on Turbo-MTP, refer to the
application note AN48864 “Performance Optimization by West
Bridge Controllers with Turbo-MTP”.
8051 Microprocessor
The 8051 microprocessor embedded in Antioch does basic
transaction management for all the transactions between the
P-port, the S-port, and the U-port. The 8051 does not reside in
the data path; it manages the path. The data path is optimized
for performance. The 8051 executes firmware that supports
NAND, SD, and MMC devices at the S-port. For the NAND
device, the 8051 firmware follows the Smart Media algorithm to
support:
Physical to Logical Management
ECC Correction
Wear Leveling
NAND Flash Bad Block Handling
Configuration and Status Registers
The West Bridge Antioch device includes Configuration and
Status registers that are accessible as memory mapped registers
through the processor interface. The Configuration registers
allow the system to specify certain behavior from Antioch. For
example, it masks certain Status registers from raising an
interrupt. The Status registers convey the status of different
parameters of Antioch, such as the addresses of buffers for read
operations.
Processor Interface (P-port)
Communication with the external processor is realized through a
dedicated processor interface. This interface supports both
synchronous and asynchronous SRAM mapped memory
accesses. This ensures straightforward electrical
communications with the processor that also has other devices
connected on a shared memory bus. Asynchronous accesses
reach a bandwidth of up to 66.7 MBps. Synchronous accesses
are performed at 33 MHz across 16 bits for up to 66.7 MBps
bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Antioch. These endpoints serve as
buffers for data between each pair of ports, for example, between
the processor port and the USB port. The processor writes and
reads into these buffers through the memory interface.
Access to these buffers is controlled by using either a DMA
protocol or an interrupt to the main processor. These two modes
are configured by the external processor.
As a DMA slave, Antioch generates a DMA request signal to
signify to the main processor that it is ready to read from or write
to a specific buffer. The external processor monitors this signal
and polls Antioch for the specific buffers ready for read or write.
It then performs the appropriate read or write operations on the
buffer through the processor interface. This way, the external
processor only deals with the buffers to access a multitude of
storage devices connected to Antioch.
In the Interrupt mode, Antioch communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Antioch for the specific
buffers ready for read or write and performs the appropriate read
or write operations through the processor interface.
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Antioch operates
in Full Speed USB mode in addition to High Speed USB mode.
The USB interface consists of the USB transceiver. The USB
interface accesses and also is accessed by both the P-port and
the S-port.
The Antioch USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Mass Storage Support (S-Port)
The S-port is configured in two different modes, either
simultaneously supporting an SD/MMC+ port and a × 8 NAND
port or supporting a unique × 16 NAND access port. The
NANDCFG Ball is used to set the configuration of the S-port as
either 16-bit NAND or 8-bit NAND and SD/MMC. The 16-bit
interface is only used when there is no other mass storage
device connected to the S-port. Note that in the WLCSP option,
the S-port is not configurable; it only supports a single SD/MMC+
port with no NAND port.
Antioch also includes two chip enables, NAND_CE# and
NAND_CE2#, that enable to access two different NANDs
alternately.
Document Number: 001-07978 Rev. *O
Page 3 of 31







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)