TetraHub Controller. CY7C65642 Datasheet

CY7C65642 Controller. Datasheet pdf. Equivalent

CY7C65642 Datasheet
Recommendation CY7C65642 Datasheet
Part CY7C65642
Description Very Low Power USB 2.0 TetraHub Controller
Feature CY7C65642; CY7C65642 HX2VL – Very Low Power USB 2.0 TetraHub™ Controller HX2VL – Very Low Power USB 2.0 TetraH.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C65642 Datasheet




Cypress Semiconductor CY7C65642
CY7C65642
HX2VL - Very Low-Power USB 2.0
TetraHub™ Controller
HX2VL - Very Low-Power USB 2.0 TetraHub™ Controller
Features
High-performance, low-power USB 2.0 hub, optimized for
low-cost designs with minimum bill-of-material (BOM).
USB 2.0 hub controller
Compliant with USB2.0 specification, TID# 30000059
Up to four downstream ports support
Downstream ports are backward compatible with FS, LS
Multiple translator (TT), one per downstream port for
maximum performance.
Very low-power consumption
Supports bus-powered and self-powered modes
Auto switching between bus-powered and self-powered
Single MCU with 2 K ROM and 64 byte RAM
Lowest power consumption.
Highly integrated solution for reduced BOM cost
Internal regulator – single power supply 5 V required.
Provision of connecting 3.3 V with external regulator.
Integrated upstream pull-up resistor
Integrated pull-down resistors for all downstream ports
Integrated upstream/downstream termination resistors
Integrated port status indicator control
12-MHz +/-500 ppm external crystal with drive level 600 W
(integrated PLL) clock input with optional 27/48-MHz
oscillator clock input.
Internal power failure detection for ESD recovery
Downstream port management
Support individual and ganged mode power management
Overcurrent detection
Two status indicators per downstream port
Maximum configurability
VID and PID are configurable through external EEPROM
Number of ports, removable/non-removable ports are
configurable through EEPROM and I/O pin configuration
I/O pins can configure gang/individual mode power
switching, reference clock source and polarity of power
switch enable pin
Configuration options also available through mask ROM
Available in space saving 48-pin TQFP (7 × 7 mm) and 28-pin
QFN (5 × 5 mm) packages
Supports 0 C to +70 C temperature range
Block Diagram
12/27/48
MHz
OSC-in
OR 12
MHz
Crystal
D+ D-
USB 2.0 PHY
PLL
USB Upstream Port
Hub Repeater
Serial
Interface
Engine
HS USB
Control Logic
MCU
RAM ROM
Transaction Translator x 4
Routing Logic
1.8 V Regulator
3.3 V
I2C /
SPI
5 V i/p (for internal
regulator)
NC (for external regulator)
3.3 V i/p (with ext. reg. & 28-QFN
NC (with ext. reg. & 48-TQFP)
3.3 V o/p (for int. reg.)
USB Downstream Port 1
USB 2.0
PHY
Port
Control
USB Downstream Port 2
USB 2.0
PHY
Port
Control
USB Downstream Port 3
USB 2.0
PHY
Port
Control
USB Downstream Port 4
USB 2.0
PHY
Port
Control
D+ D-
LED D+ D-
LED D+ D-
LED D+ D-
LED
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65659 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 13, 2018



Cypress Semiconductor CY7C65642
CY7C65642
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right HX2VL device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
http://www.cypress.com/?id=2411.
Overview: USB Portfolio, USB Roadmap
USB 2.0 Hub Controller Selectors: HX2LP, HX2VL
Application notes: Cypress offers a large number of USB appli-
cation notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with HX2VL are:
AN72332 - Guidelines on System Design using Cypress's
USB 2.0 Hub (HX2VL)
AN69235 - Migrating from HX2/HX2LP to HX2VL
Reference Designs:
CY4608 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
CY4607 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
Models: HX2VL (CY7C65632/34/42) - IBIS
HX2VL Development Kit
HX2VL Development Kit board is a tool to demonstrate the features of HX2VL devices (CY7C65632, CY7C65634). In the initial phase
of the design, this board helps developers to understand the chip features and limitations before proceeding with a complete design.
The Development kit includes support documents related to board hardware, PC application software, and EEPROM configuration
data (.iic) files.
Document Number: 001-65659 Rev. *K
Page 2 of 26



Cypress Semiconductor CY7C65642
CY7C65642
Contents
Introduction ....................................................................... 4
HX2VL Architecture .......................................................... 4
USB Serial Interface Engine ........................................ 4
HS USB Control Logic ................................................. 4
Hub Repeater .............................................................. 4
MCU ............................................................................ 4
Transaction Translator ................................................ 4
Port Control ................................................................. 4
Applications ...................................................................... 4
Functional Overview ........................................................ 5
System Initialization ..................................................... 5
Enumeration ................................................................ 5
Multiple Transaction Translator Support ..................... 5
Upstream Port ............................................................. 5
Downstream Ports ....................................................... 5
Power Switching .......................................................... 5
Overcurrent Detection ................................................. 5
Port Indicators ............................................................. 5
Power Regulator .......................................................... 6
External Regulation Scheme ....................................... 6
Internal Regulation Scheme ........................................ 6
Pin Configurations ........................................................... 7
Pin Definitions .................................................................. 9
Pin Definitions ................................................................ 12
EEPROM Configuration Options ................................... 14
Pin Configuration Options ............................................. 15
Power ON Reset ....................................................... 15
Gang/Individual Power Switching Mode .................... 15
Power Switch Enable Pin Polarity ............................. 15
Port Number Configuration ........................................ 15
Non Removable Ports Configuration.......................... 15
Reference Clock Configuration ................................. 15
Absolute Maximum Ratings .......................................... 16
Operating Conditions..................................................... 16
Electrical Characteristics ............................................... 17
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 18
Thermal Resistance ........................................................ 18
Ordering Information...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Silicon Errata for the HX2VL, CY7C65642 Product
Family ............................................................................. 23
Part Numbers Affected .............................................. 23
HX2VL Qualification Status ....................................... 23
HX2VL Errata Summary ............................................ 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Document Number: 001-65659 Rev. *K
Page 3 of 26







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