Bridge Controller. CYUSB3610 Datasheet

CYUSB3610 Controller. Datasheet pdf. Equivalent

CYUSB3610 Datasheet
Recommendation CYUSB3610 Datasheet
Part CYUSB3610
Description SuperSpeed USB to Gigabit Ethernet Bridge Controller
Feature CYUSB3610; CYUSB3610 EZ-USB GX3: SuperSpeed USB to Gigabit Ethernet Bridge Controller EZ-USB GX3: SuperSpeed U.
Manufacture Cypress Semiconductor
Datasheet
Download CYUSB3610 Datasheet




Cypress Semiconductor CYUSB3610
CYUSB3610
EZ-USB GX3: SuperSpeed USB
to Gigabit Ethernet Bridge Controller
EZ-USB GX3: SuperSpeed USB to Gigabit Ethernet Bridge Controller
Features
Low-power single chip USB 3.0 to 10/100/1000M Gigabit
Ethernet Bridge Controller with Energy Efficient Ethernet (EEE)
Gigabit Ethernet Controller
Supports IEEE 802.3az (Energy Efficient Ethernet)
IEEE 802.3, 802.3u, and 802.3ab compatible
Integrates 10/100/1000Mbps Gigabit Ethernet MAC/PHY
Supports dynamic cable length detection and dynamic power
adjustment Green Ethernet (Gigabit mode only)
Supports parallel detection and automatic polarity correction
Supports crossover detection and auto-correction
Supports IPv4/IPv6 packet Checksum Offload Engine
(COE)
to reduce CPU loading, including IPv4
IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICMPv6
checksum check & generation
Supports TCP Large Send Offload V1
Supports full duplex operation with IEEE 802.3x flow control
and half duplex operation with back-pressure flow control.
Supports IEEE 802.1P Layer 2 Priority Encoding and
Decoding
Supports IEEE 802.1Q VLAN tagging and 2 VLAN ID filtering;
received VLAN Tag (4 bytes) can be stripped off or preserved
Supports Jumbo frame
PHY loop-back diagnostic capability
USB Device Controller
Integrates on-chip USB 3.0 PHY and controller
Supports USB 3.0 power saving modes (U0, U1, U2, and U3)
High performance packet transfer rate over USB bus using
burst transfer mechanism
Advanced Power Management Features
Supports power management offload (ARP & NS)
Supports dynamic power management to reduce power
dissipation during idle or light traffic
Supports AutoDetach power saving. Soft-disconnect from
USB host when Ethernet cable is unplugged
Supports advanced link down power saving when Ethernet
cable is unplugged
Wake-on-LAN Feature
Supports suspend mode and remote wakeup via link-change,
Magic Packet, Microsoft wakeup frame and external wakeup
pin
Supports Bonjour wake-on-demand
Supports serial EEPROM (93C56/66) for storing USB
Descriptors, Node-ID, etc
Supports automatic loading of USB Device Descriptors,
Node-ID, etc. from internal memory or external EEPROM after
power-on initialization
Single 25 MHz clock input from crystal or oscillator source
Integrates on-chip power-on reset circuit
Integrates pipelined RISC SoC (System on Chip) for handling
protocol and control functions
68-pin QFN 8 mm × 8 mm RoHS/REACH compliant package
Operating temperature: 0 °C to 70 °C
Target Applications
Docking Station
USB Dongle
Embedded systems
Network Printer
USB Port Replicator
POS, Card Reader
Netbook, UMPC, MID
Ultrabook
IP STB, IP TV
Gaming Console
Functional Description
The GX3 SuperSpeed USB to 10/100/1000M Gigabit Ethernet
Bridge Controller is a high-performance and highly integrated
controller that enables low-cost design, small form-factor, and
simple plug-and-play Gigabit Ethernet network connection
capability for docking stations, desktops, notebook PCs,
Ultrabooks, gaming consoles, digital-home appliances, and any
embedded system using a standard USB port.
GX3 implements a 10/100/1000Mbps Ethernet LAN function
based on IEEE802.3, IEEE802.3u, and IEEE802.3ab standards
with embedded SRAMs for packet buffering. It also integrates an
on-chip 10/100/1000Mbps EEE-compliant Ethernet PHY to
simplify system design. It features a USB interface to
communicate with a USB Host Controller and is compliant with
USB specification v3.0.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94768 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 31, 2018



Cypress Semiconductor CYUSB3610
Block Diagram
XTALIN
XTALOUT
MFA[3:0],
GPIO[3:0]
CS
SCK
SDA
RESET#
Reset
PLL
oscillator
ROM
Pipelined
RISC
Data
RAM
DMA
Engine
GPIOs,
LEDs
Serial
EEPROM
interface
DP/DM
SSTXP(M)
SSRXP(M)
USB
3.0
PHY
SRAM
buffer
USB
3.0
core
SuperSpeed USB to
Gigabit Ethernet
Bridge
Gigabit
Ethernet
PHY
Memory
Arbiter
Checksum
Offload
Engine
GMAC
core
CYUSB3610
MDIP[3:0]
MDIN[3:0]
Document Number: 001-94768 Rev. *C
Page 2 of 35



Cypress Semiconductor CYUSB3610
CYUSB3610
Contents
Pin Configurations ........................................................... 4
Signal Description ............................................................ 5
Pin Description ................................................................. 5
Settings ............................................................................. 8
Hardware Setting
for Operation Mode and Multi-Function Pins ...................... 8
Functional Overview ........................................................ 9
USB Core and Interfaces ............................................ 9
Energy Efficient Ethernet (EEE) .................................. 9
10/100/1000M Ethernet PHY ...................................... 9
MAC Core .................................................................... 9
Checksum Offload Engine (COE) ............................... 9
Memory Arbiter ............................................................ 9
USB to Ethernet Bridge ............................................... 9
SEEPROM Loader Interface ..................................... 10
GPIOs and LED ......................................................... 10
PLL Clock Generator ................................................. 10
Reset Generation ...................................................... 10
Default Wake-On-LAN (DWOL) Ready Mode ................ 11
Procedure to Enable Default WOL Ready Mode ....... 11
Flow Chart of Default WOL Ready Mode .................. 13
Serial EEPROM Memory Map ........................................ 14
Detailed Description .................................................. 15
USB Configuration Structure ........................................ 20
Electrical Specifications ................................................ 21
DC Characteristics .................................................... 21
Thermal Characteristics ............................................ 24
Power Consumption .................................................. 25
Power-up Sequence .................................................. 27
AC Timing Characteristics ......................................... 28
Package Information ...................................................... 30
68-pin QFN 8 × 8 package ........................................ 30
Recommended PCB Footprint
for 68-pin QFN 8x8 package ............................................ 31
Ordering Information ...................................................... 32
Acronyms ........................................................................ 33
Document Conventions ................................................. 33
Units of measure ....................................................... 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Document Number: 001-94768 Rev. *C
Page 3 of 35







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