Voltage Microcontroller. CY7C64013 Datasheet

CY7C64013 Microcontroller. Datasheet pdf. Equivalent

CY7C64013 Datasheet
Recommendation CY7C64013 Datasheet
Part CY7C64013
Description Low Voltage Microcontroller
Feature CY7C64013;  CY7C604XX enCoRe™ V Low Voltage Microcontroller Features ■ Powerful Harvard Architecture processo.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C64013 Datasheet




Cypress Semiconductor CY7C64013
CY7C604XX
enCoRe™ V Low Voltage Microcontroller
enCoRe™ V Low Voltage Microcontroller
Features
Powerful Harvard Architecture processor
M8C processor speeds running up to 24 MHz
Low power at high processing speeds
Interrupt controller
1.71 V to 3.6 V operating voltage
Commercial temperature range: 0 °C to +70 °C
Flexible on-chip memory
Up to 32 K flash program storage
• 50,000 erase and write cycles
• Flexible protection modes
Up to 2048 bytes SRAM data storage
In-system serial programming (ISSP)
Complete development tools
Free development tool (PSoC® Designer™)
Full-featured, in-circuit emulator and programmer
Full-speed emulation
Complex breakpoint structure
128 K trace memory
Precision, programmable clocking
Crystal-less oscillator with support for an external crystal or
resonator
Internal ±5.0% 6, 12, or 24 MHz main oscillator
enCoRe V LV Block Diagram
Internal low-speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
Programmable pin configurations
Up to 36 GPIO (depending on package)
25 mA sink current on all GPIO
Pull-up, High Z, open drain, CMOS drive modes on all GPIO
CMOS drive mode (5 mA source current) on Ports 0 and 1:
• 20 mA (at 3.0 V) total source current
Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
Selectable, regulated digital I/O on Port 1
Configurable input threshold for Port 1
Hot-swappable capability on Port 1
Additional system resources
Configurable communication speeds
I2C Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
SPI master and SPI slave
• Configurable between 46.9 kHz and 12 MHz
Three 16-bit timers
10-bit ADC used to monitor battery voltage or other signals
with external components
Watchdog and sleep timers
Integrated supervisory circuit
enCoRe V
CORE
SRAM
2048 Bytes
Interrupt
Controller
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO
SROM
8 K / 16 K / 32 K
Flash
CPU Core (M8C)
System Bus
Sleep and
Watchdog
6 / 12 / 24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
System Resources
Errata: For information on silicon errata, see “Errata” on page 35. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12395 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 10, 2017



Cypress Semiconductor CY7C64013
CY7C604XX
Contents
Functional Overview ........................................................ 3
The enCoRe V LV Core .............................................. 3
10-bit ADC ................................................................... 3
SPI ............................................................................... 4
I2C Slave ..................................................................... 4
Additional System Resources ..................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pin Configuration ............................................................. 8
16-Pin Part Pinout ....................................................... 8
32-Pin Part Pinout ....................................................... 9
48-Pin Part Pinout ..................................................... 11
Register Reference ......................................................... 13
Register Conventions .................................................... 13
Register Mapping Tables ............................................... 13
Electrical Specifications ................................................ 16
Absolute Maximum Ratings ....................................... 17
Operating Temperature ............................................. 17
DC Electrical Characteristics ..................................... 18
AC Electrical Characteristics ..................................... 24
Package Diagrams .......................................................... 29
Packaging Dimensions .............................................. 29
Thermal Impedances ...................................................... 32
Capacitance on Crystal Pins ......................................... 32
Solder Reflow Peak Temperature ................................. 32
Ordering Information ...................................................... 33
Ordering Code Definitions ......................................... 33
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Errata ............................................................................... 35
CY7C604xx Errata Summary .................................... 35
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support ....................... 39
Products .................................................................... 39
PSoC® Solutions ...................................................... 39
Cypress Developer Community ................................. 39
Technical Support ..................................................... 39
Document Number: 001-12395 Rev. *Q
Page 2 of 39



Cypress Semiconductor CY7C64013
CY7C604XX
Functional Overview
The enCoRe V LV family of devices are designed to replace
multiple traditional low voltage microcontroller system compo-
nents with one, low cost single chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts.
The architecture for this device family, as illustrated in enCoRe
V LV Block Diagram, is comprised of two main areas: the CPU
core and the system resources. Depending on the enCoRe V LV
package, up to 36 GPIO are also included.
Enhancements over the Cypress’s legacy low-voltage microcon-
trollers include faster CPU at lower voltage operation, lower
current consumption, twice the RAM and flash, hot-swapable
I/Os, I2C hardware address recognition, new very low-current
sleep mode, and new package options.
The enCoRe V LV Core
The enCoRe V LV Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low-speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as a
configurable I2C slave and SPI master-slave communication
interface and various system resets supported by the M8C.
10-bit ADC
The ADC on enCoRe V LV device is an independent block with
a state machine interface to control accesses to the block. The
ADC is housed together with the temperature sensor core and
can be connected to this or the Analog Mux Bus. As a default
operation, the ADC is connected to the temperature sensor
diodes to give digital values of the temperature.
Figure 1. ADC System Performance Block Diagram
VIN
TEMP SENSOR/ ADC
TEMP
DIODES
ADC
SYSTEM BUS
INTERFACE BLOCK
COMMAND/ STATUS
Interface to the M8 C
( Processor ) Core
The ADC User Module contains an integrator block and one
comparator with positive and negative input set by the MUXes.
The input to the integrator stage comes from the Analog Global
Input Mux or the temperature sensor with an input voltage range
of 0 V to 1.3 V, where 1.3 V is 72% of full scale.
In the ADC only configuration (the ADC MUX selects the Analog
Mux Bus, not the default temperature sensor connection), an
external voltage can be connected to the input of the modulator
for voltage conversion. The ADC is run for a number of cycles
set by the timer, depending upon the resolution of the ADC
desired by the user. A counter counts the number of trips by the
comparator, which is proportional to the input voltage. The Temp
Sensor block clock speed is 36 MHz and is divided down to 1 to
12 MHz for ADC operation.
Document Number: 001-12395 Rev. *Q
Page 3 of 39







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