Peripheral Interface. S25FS512S Datasheet

S25FS512S Interface. Datasheet pdf. Equivalent

S25FS512S Datasheet
Recommendation S25FS512S Datasheet
Part S25FS512S
Description 512 Mbit / 1.8 V Serial Peripheral Interface
Feature S25FS512S; S25FS512S 512 Mbit, 1.8 V Serial Peripheral Interface with Multi-I/O Flash Features  Serial Periph.
Manufacture Cypress Semiconductor
Datasheet
Download S25FS512S Datasheet




Cypress Semiconductor S25FS512S
S25FS512S
512 Mbit, 1.8 V Serial Peripheral Interface
with Multi-I/O Flash
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing – 24 or 32-bit address options
– Serial Command subset and footprint compatible with
S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
– Multi I/O Command subset and footprint compatible with
S25FL-P, and S25FL-S SPI families
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad
I/O
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) and
Common Flash Interface (CFI), for configuration
information.
Program
– 256 or 512 Bytes Page Programming buffer
– Program suspend and resume
– Automatic Error Checking and Correction (ECC) – internal
hardware ECC with single bit error correction
Erase
– Hybrid sector option
– Physical set of eight 4-kbytes sectors and one
224-kbytes sector at the top or bottom of address
space with all remaining sectors of 256 kbytes
– Uniform sector option
– Uniform 256 kbyte blocks
– Erase suspend and resume
– Erase status evaluation
– 100,000 Program-Erase Cycles
– 20 Year Data Retention
Security Features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
– Option for password control of read access
Technology
– Cypress 65-nm MirrorBitTechnology with Eclipse
Architecture
Supply Voltage
– 1.7 V to 2.0 V
Temperature Range / Grade
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC 300 mil (SO3016)
– WSON 6x8 mm (WNH008)
– BGA-24 6 8 mm
– 5 5 ball (FAB024) footprint
– Known Good Die and Known Tested Die
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00488 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 03, 2016



Cypress Semiconductor S25FS512S
Performance Summary
Maximum Read Rates
Read
Fast Read
Dual Read
Quad Read
DDR Quad I/O Read
Command
Typical Program and Erase Rates
Operation
Page Programming (256-bytes page buffer)
Page Programming (512-bytes page buffer)
4-kbytes Physical Sector Erase (Hybrid Sector Option)
256-kbytes Sector Erase (Uniform Logical Sector Option)
Typical Current Consumption, 40°C to +85°C
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 133 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Deep Power Down
Operation
S25FS512S
Clock Rate (MHz)
50
133
133
133
80
Mbytes/s
6.25
16.5
33
66
80
kbytes/s
712
1080
28
250
Current (mA)
10
20
60
70
60
60
0.07
0.006
Document Number: 002-00488 Rev. *E
Page 2 of 143



Cypress Semiconductor S25FS512S
S25FS512S
Contents
1. Overview ....................................................................... 4
1.1 General Description ....................................................... 4
1.2 Migration Notes.............................................................. 4
1.3 Glossary......................................................................... 7
1.4 Other Resources............................................................ 7
Hardware Interface
2. Signal Descriptions ..................................................... 8
2.1 Input/Output Summary................................................... 8
2.2 Multiple Input / Output (MIO).......................................... 9
2.3 Serial Clock (SCK) ......................................................... 9
2.4 Chip Select (CS#) .......................................................... 9
2.5 Serial Input (SI) / IO0 ..................................................... 9
2.6 Serial Output (SO) / IO1................................................. 9
2.7 Write Protect (WP#) / IO2 ............................................ 10
2.8 IO3 / RESET# ............................................................. 10
2.9 Voltage Supply (VDD)................................................... 10
2.10 Supply and Signal Ground (VSS) ................................. 10
2.11 Not Connected (NC) .................................................... 11
2.12 Reserved for Future Use (RFU)................................... 11
2.13 Do Not Use (DNU) ....................................................... 11
2.14 Block Diagrams............................................................ 12
3. Signal Protocols......................................................... 14
3.1 SPI Clock Modes ......................................................... 14
3.2 Command Protocol ...................................................... 15
3.3 Interface States............................................................ 19
3.4 Configuration Register Effects on the Interface ........... 23
3.5 Data Protection ............................................................ 23
4. Electrical Specifications............................................ 24
4.1 Absolute Maximum Ratings ......................................... 24
4.2 Thermal Resistance ..................................................... 24
4.3 Latchup Characteristics ............................................... 24
4.4 Operating Ranges........................................................ 24
4.5 Power-Up and Power-Down ........................................ 25
4.6 DC Characteristics ....................................................... 27
5. Timing Specifications ................................................ 30
5.1 Key to Switching Waveforms ....................................... 30
5.2 AC Test Conditions ...................................................... 30
5.3 Reset............................................................................ 31
5.4 SDR AC Characteristics............................................... 34
5.5 DDR AC Characteristics. ............................................. 36
6. Physical Interface ...................................................... 39
6.1 SOIC 16-Lead Package ............................................... 39
6.2 8-Connector Package .................................................. 41
6.3 BGA 24-Ball, 5x5 Ball Footprint (FAB024).................... 43
Software Interface
7. Address Space Maps .................................................. 45
7.1 Overview....................................................................... 45
7.2 Flash Memory Array...................................................... 45
7.3 ID-CFI Address Space .................................................. 46
7.4 JEDEC JESD216 Serial Flash
Discoverable Parameters (SFDP) Space ..................... 46
7.5 OTP Address Space ..................................................... 47
7.6 Registers....................................................................... 48
8. Data Protection ........................................................... 65
8.1 Secure Silicon Region (OTP)........................................ 65
8.2 Write Enable Command................................................ 66
8.3 Block Protection ............................................................ 66
8.4 Advanced Sector Protection ......................................... 67
8.5 Recommended Protection Process .............................. 73
9. Commands .................................................................. 74
9.1 Command Set Summary............................................... 75
9.2 Identification Commands .............................................. 80
9.3 Register Access Commands......................................... 83
9.4 Read Memory Array Commands .................................. 94
9.5 Program Flash Array Commands ............................... 102
9.6 Erase Flash Array Commands.................................... 104
9.7 One Time Program Array Commands ........................ 111
9.8 Advanced Sector Protection Commands .................... 111
9.9 Reset Commands ....................................................... 117
9.10 DPD Commands ......................................................... 119
10. Embedded Algorithm Performance Tables ............ 121
11. Data Integrity ............................................................. 121
11.1 Erase Endurance ........................................................ 121
11.2 Data Retention ............................................................ 121
11.3 Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 122
11.4 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 124
11.5 Initial Delivery State .................................................... 138
Ordering Information
12. Ordering Part Number .............................................. 139
13. Contact....................................................................... 140
14. Revision History........................................................ 141
Document Number: 002-00488 Rev. *E
Page 3 of 143







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)