16 nvSRAM. CY14B116M Datasheet

CY14B116M nvSRAM. Datasheet pdf. Equivalent

CY14B116M Datasheet
Recommendation CY14B116M Datasheet
Part CY14B116M
Description 16-Mbit (2048 K x 8/1024 K x 16) nvSRAM
Feature CY14B116M; CY14B116K/CY14B116M 16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with Real Time Clock Features ■ 16-Mbit.
Manufacture Cypress Semiconductor
Datasheet
Download CY14B116M Datasheet




Cypress Semiconductor CY14B116M
CY14B116K/CY14B116M
16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with
Real Time Clock
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14B116K),
1024 K × 16 (CY14B116M)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Full-featured real time clock (RTC)
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 A (typical)
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 750 A
Sleep mode current of 10 A
Operating voltage: VCC = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14B116K/CY14B116M combines a 16-Mbit
nvSRAM with a full-featured RTC in a monolithic integrated
circuit. The nvSRAM is a fast SRAM with a nonvolatile element
in each memory cell. The memory is organized as 2048 K bytes
of 8 bits each or 1024 K words of 16 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data residing in the nonvolatile elements do not
change when data is written to the SRAM. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL operations
are also available under software control.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high-accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67786 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015



Cypress Semiconductor CY14B116M
CY14B116K/CY14B116M
Logic Block Diagram[1, 2, 3]
A0-A11
VCC VCAP VRTCcap VRTCbat
QUANTUMTRAP
4096 X 4096
STORE
STATIC RAM
ARRAY
4096 X 4096
RECALL
POWER CONTROL
SLEEP MODE
CONTROL
ZZ
STORE / RECALL
CONTROL
HSB
SOFTWARE
DETECT
A2-A14
OE [4]
CE
WE
DQ 0-DQ 15
COLUMN IO
COLUMN DECODER
A12-A20
BLE
BHE
ZZ
RTC
X out
X in
INT
MUX
A0-A20
Notes
1. Address A0–A20 for ×8 configuration and address A0–A19 for ×16 configuration.
2. Data DQ0–DQ7 for ×8 configuration and data DQ0–DQ15 for ×16 configuration.
3. BLE, BHE are applicable for x16 configuration.
4. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Document #: 001-67786 Rev. *J
Page 2 of 42



Cypress Semiconductor CY14B116M
CY14B116K/CY14B116M
Contents
Pinouts .............................................................................. 4
Device Operation .............................................................. 6
SRAM Read ....................................................................... 6
SRAM Write ....................................................................... 6
AutoStore Operation (Power-Down) ............................... 6
Hardware STORE (HSB) Operation................................. 7
Hardware RECALL (Power-Up) ....................................... 7
Software STORE ............................................................... 7
Software RECALL............................................................. 7
Sleep Mode........................................................................ 8
Preventing AutoStore....................................................... 9
Data Protection ............................................................... 10
Real Time Clock Operation............................................ 10
nvTime Operation...................................................... 10
Clock Operations....................................................... 10
Reading the Clock ..................................................... 10
Setting the Clock ....................................................... 10
Backup Power ........................................................... 10
Stopping and Starting the Oscillator.......................... 11
Calibrating the Clock ................................................. 11
Alarm ......................................................................... 11
Watchdog Timer ........................................................ 12
Programmable Square Wave Generator................... 12
Power Monitor ........................................................... 12
Backup Power Monitor .............................................. 13
Interrupts ................................................................... 13
Flags Register ........................................................... 14
RTC External Components ....................................... 15
PCB Design Considerations for RTC............................ 15
Layout Requirements ................................................ 15
Maximum Ratings........................................................... 22
Operating Range............................................................. 22
DC Electrical Characteristics ........................................ 22
Data Retention and Endurance ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance........................................................ 23
AC Test Conditions ........................................................ 24
RTC Characteristics ....................................................... 24
AC Switching Characteristics ....................................... 25
AutoStore/Power-Up RECALL Characteristics............ 29
Sleep Mode Characteristics........................................... 30
Software Controlled STORE and RECALL
Characteristics................................................................ 31
Hardware STORE Characteristics................................. 32
For ×16 Configuration ............................................... 33
Truth Table For SRAM Operations................................ 33
For ×8 Configuration ................................................. 33
For ×16 Configuration ............................................... 34
Ordering Information...................................................... 35
Package Diagrams.......................................................... 36
Acronyms ........................................................................ 39
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Errata ............................................................................... 40
Part Numbers Affected .............................................. 40
16-Mbit (2048 K × 8, 1024 K × 16) nvSRAM
Qualification Status ................................................... 40
16-Mbit (2048 K × 8, 1024 K × 16) nvSRAM
Errata Summary ........................................................ 40
Document History Page ................................................. 42
Sales, Solutions, and Legal Information ...................... 44
Worldwide Sales and Design Support....................... 44
Products .................................................................... 44
PSoC® Solutions ...................................................... 44
Cypress Developer Community................................. 44
Technical Support ..................................................... 44
Document #: 001-67786 Rev. *J
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