NAND Flash. S34MS01G2 Datasheet

S34MS01G2 Flash. Datasheet pdf. Equivalent

S34MS01G2 Datasheet
Recommendation S34MS01G2 Datasheet
Part S34MS01G2
Description 1 Gbit/2 Gbit/4 Gbit SLC NAND Flash
Feature S34MS01G2; S34MS01G2 S34MS02G2 S34MS04G2 1 Gbit/2 Gbit/4 Gbit SLC NAND Flash for Embedded Distinctive Characte.
Manufacture Cypress Semiconductor
Datasheet
Download S34MS01G2 Datasheet




Cypress Semiconductor S34MS01G2
S34MS01G2
S34MS02G2
S34MS04G2
1 Gbit/2 Gbit/4 Gbit
SLC NAND Flash for Embedded
Distinctive Characteristics
Density
– 1 Gb / 2 Gb / 4 Gb
Architecture
– Input / Output Bus Width: 8 bits / 16 bits
– Page size:
– x8
1 Gb: (2048 + 64) bytes; 64-byte spare area
2 Gb / 4 Gb: (2048 + 128) bytes; 128-byte spare area
– x16
1 Gb: (1024 + 32) words; 32-word spare area
2 Gb / 4Gb: (1024 + 64) words; 64-word spare area
– Block size: 64 Pages
– x8
1 Gb: 128 KB + 4 KB
2 Gb / 4 Gb: 128 KB + 8 KB
– x16
1 Gb: (64k + 2k) words
2 Gb / 4 Gb: (64k + 4k) words
– Plane size:
– x8
1 Gb: 1024 Blocks per Plane or (128 MB + 4 MB)
2 Gb: 1024 Blocks per Plane or (128 MB + 8 MB)
4 Gb: 2048 Blocks per Plane or (256 MB + 16 MB)
– x16
1 Gb: 1024 Blocks per Plane or (64M + 2M) words
2 Gb: 1024 blocks per plane or (64M + 4M) words
4 Gb: 2048 blocks per plane or (128M + 8M) words
– Device size:
– 1 Gb: 1 plane per device or 128 MB
– 2 Gb: 2 planes per device or 256 MB
– 4 Gb: 2 planes per device or 512 MB
NAND flash interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data, and Commands multiplexed
Supply voltage
– 1.8 V device: VCC = 1.7 V ~ 1.95 V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID) (Contact factory for support)
– Hardware program/erase disabled during power transition
Additional features
– 2 Gb and 4 Gb parts support Multiplane Program and
Erase commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back
Program
– Supports Read Cache
Electronic signature
– Manufacturer ID: 01h
Operating temperature
– Industrial: 40 °C to 85 °C
– Industrial Plus: 40 °C to 105 °C
Performance
Page Read / Program
– Random access: 25 µs (Max) (S34MS01G2)
– Random access: 30 µs (Max) (S34MS02G2, S34ML04G2)
– Sequential access: 45 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase (S34MS01G2)
– Block Erase time: 3.0 ms (Typ)
Block Erase / Multiplane Erase (S34MS02G2, S34MS04G2)
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes (x8) or 264 words (x16))
– 10-year Data retention (Typ)
– For one plane structure (1-Gb density)
– Block zero is valid and will be valid for at least 1,000
program-erase cycles with ECC
– For two plane structures (2-Gb and 4-Gb densities)
– Blocks zero and one are valid and will be valid for at
least 1,000 program-erase cycles with ECC
Package options
– Pb-free and Low Halogen
– 48-Pin TSOP 12 20 1.2 mm
– 63-Ball BGA 9 11 1 mm
– 67-Ball BGA 8 6.5 1 mm (S34MS01G2, S34MS02G2)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-03238 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2016



Cypress Semiconductor S34MS01G2
S34MS01G2
S34MS02G2
S34MS04G2
Contents
1. General Description...................................................... 3
1.1 Logic Diagram .................................................. 4
1.2 Connection Diagram......................................... 5
1.3 Pin Description ................................................. 7
1.4 Block Diagram .................................................. 8
1.5 Array Organization............................................ 9
1.6 Addressing...................................................... 11
1.6.1 S34MS01G211
1.6.2 S34MS02G212
1.6.3 S34MS04G213
1.7 Mode Selection............................................... 14
2. Bus Operation ............................................................. 15
2.1 Command Input .............................................. 15
2.2 Address Input ................................................. 15
2.3 Data Input ....................................................... 15
2.4 Data Output .................................................... 15
2.5 Write Protect................................................... 15
2.6 Standby .......................................................... 15
3. Command Set.............................................................. 16
3.1 Page Read...................................................... 17
3.2 Page Program ................................................ 17
3.3 Multiplane Program
— S34MS02G2 and S34MS04G2.................. 18
3.4 Page Reprogram ............................................ 18
3.5 Block Erase .................................................... 20
3.6 Multiplane Block Erase
— S34MS02G2 and S34MS04G2.................. 20
3.7 Copy Back Program ....................................... 21
3.8 Read Status Register ..................................... 22
3.9 Read Status Enhanced
— S34MS02G2 and S34MS04G2.................. 22
3.10 Read Status Register Field Definition............. 22
3.11 Reset .............................................................. 23
3.12 Read Cache.................................................... 23
3.13 Cache Program .............................................. 24
3.14 Multiplane Cache Program
— S34MS02G2 and S34MS04G2.................. 25
3.15 Read ID .......................................................... 26
3.16 Read ID2 ........................................................ 28
3.17 Read ONFI Signature ..................................... 28
3.18 Read Parameter Page.................................... 28
3.19 Read Unique ID (Contact Factory) ................. 31
3.20 One-Time Programmable (OTP) Entry........... 32
4. Signal Descriptions .................................................... 33
4.1 Data Protection and Power
On / Off Sequence.......................................... 33
4.2 Ready/Busy .................................................... 33
4.3 Write Protect Operation .................................. 34
5. Electrical Characteristics ........................................... 35
5.1 Valid Blocks .................................................... 35
5.2 Absolute Maximum Ratings............................ 35
5.3 AC Test Conditions......................................... 35
5.4 AC Characteristics.......................................... 36
5.5 DC Characteristics.......................................... 37
5.6 Pin Capacitance ............................................. 38
5.7 Program / Erase Characteristics..................... 38
6. Timing Diagrams......................................................... 39
6.1 Command Latch Cycle ................................... 39
6.2 Address Latch Cycle ...................................... 40
6.3 Data Input Cycle Timing ................................. 40
6.4 Data Output Cycle Timing
(CLE=L, WE#=H, ALE=L, WP#=H) ................ 41
6.5 Data Output Cycle Timing
(EDO Type, CLE=L, WE#=H, ALE=L)............ 41
6.6 Page Read Operation..................................... 42
6.7 Page Read Operation
(Interrupted by CE#) ....................................... 43
6.8 Page Read Operation
Timing with CE# Don’t Care ........................... 44
6.9 Page Program Operation ............................... 44
6.10 Page Program Operation
Timing with CE# Don’t Care ........................... 45
6.11 Page Program Operation
with Random Data Input ................................. 45
6.12 Random Data Output In a Page ..................... 46
6.13 Multiplane Page Program Operation
— S34MS02G2 and S34MS04G2.................. 46
6.14 Block Erase Operation ................................... 47
6.15 Multiplane Block Erase
— S34MS02G2 and S34MS04G2.................. 48
6.16 Copy Back Read with Optional
Data Readout ................................................. 49
6.17 Copy Back Program Operation
With Random Data Input ................................ 49
6.18 Multiplane Copy Back Program
— S34MS02G2 and S34MS04G2.................. 50
6.19 Read Status Register Timing.......................... 51
6.20 Read Status Enhanced Timing....................... 52
6.21 Reset Operation Timing ................................. 52
6.22 Read Cache ................................................... 53
6.23 Cache Program .............................................. 55
6.24 Multiplane Cache Program
— S34MS02G2 and S34MS04G2.................. 56
6.25 Read ID Operation Timing.............................. 58
6.26 Read ID2 Operation Timing............................ 58
6.27 Read ONFI Signature Timing ......................... 59
6.28 Read Parameter Page Timing ........................ 59
6.29 Read Unique ID Timing (Contact Factory) ..... 60
6.30 OTP Entry Timing ........................................... 60
6.31 Power On and Data Protection Timing ........... 61
6.32 WP# Handling ................................................ 62
7. Physical Interface ....................................................... 63
7.1 Physical Diagram ........................................... 63
8. System Interface ......................................................... 66
9. Error Management ...................................................... 68
9.1 System Bad Block Replacement .................... 68
9.2 Bad Block Management ................................. 69
10. Ordering Information .................................................. 70
11. Document History ....................................................... 71
Sales, Solutions, and Legal Information ........................... 75
Document Number: 002-03238 Rev. *D
Page 2 of 75



Cypress Semiconductor S34MS01G2
S34MS01G2
S34MS02G2
S34MS04G2
1. General Description
The Cypress S34MS01G2, S34MS02G2, and S34MS04G2 series is offered in 1.8 VCC and VCCQ power supply, and with x8 or x16
I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is
(2048 + spare) bytes; for x16 (1024 + spare) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2 KB (x8), or 1 kword (x16) in 300 µs and an erase
operation can typically be performed in 3 ms (S34MS01G2) on a 128-kB block (x8) or 64-kword block (x16). In addition, thanks to
multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per
plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 45 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-
programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-
program operations.
Document Number: 002-03238 Rev. *D
Page 3 of 75







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