Flow-Through SRAM. CY7C1471BV33 Datasheet

CY7C1471BV33 SRAM. Datasheet pdf. Equivalent

CY7C1471BV33 Datasheet
Recommendation CY7C1471BV33 Datasheet
Part CY7C1471BV33
Description 72-Mbit (2 M x 36/4 M x 18) Flow-Through SRAM
Feature CY7C1471BV33; CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1471BV33 Datasheet




Cypress Semiconductor CY7C1471BV33
CY7C1471BV33
CY7C1473BV33
72-Mbit (2 M × 36/4 M × 18) Flow-Through
SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
No bus latency™ (NoBL™) architecture eliminates dead cycles
between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O supply (VDDQ)
Fast clock-to-output times
6.5 ns (for 133 MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball
fine-pitch ball grid array (FBGA) package. CY7C1473BV33
available in JEDEC-standard Pb-free 100-pin thin quad flat
pack (TQFP)
Three chip enables (CE1, CE2, CE3) for simple depth
expansion
Automatic power-down feature available using ZZ mode or CE
deselect
IEEE 1149.1 JTAG boundary scan compatible
Burst capability – linear or interleaved burst order
Low standby power
Functional Description
The CY7C1471BV33 and CY7C1473BV33 are 3.3 V,
2 M × 36/4 M × 18 synchronous flow through burst SRAMs
designed specifically to support unlimited true back-to-back read
or write operations without the insertion of wait states. The
CY7C1471BV33 and CY7C1473BV33 are equipped with the
advanced No Bus Latency (NoBL) logic. NoBL™ is required to
enable consecutive read or write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
6.5
305
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15029 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 17, 2014



Cypress Semiconductor CY7C1471BV33
CY7C1471BV33
CY7C1473BV33
Logic Block Diagram – CY7C1471BV33
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BW A
BW B
BW C
BW D
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
DQP C
DQP D
Logic Block Diagram – CY7C1473BV33
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BW A
BW B
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
SLEEP
CONTROL
DQs
DQP A
DQP B
Document Number: 001-15029 Rev. *I
Page 2 of 32



Cypress Semiconductor CY7C1471BV33
CY7C1471BV33
CY7C1473BV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Truth Table for Read/Write ............................................ 11
Truth Table for Read/Write ............................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing ...................................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Exit Order ............................................. 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-15029 Rev. *I
Page 3 of 32







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)