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Pipelined SRAM. CY7C1462KVE33 Datasheet

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Pipelined SRAM. CY7C1462KVE33 Datasheet
















CY7C1462KVE33 SRAM. Datasheet pdf. Equivalent













Part

CY7C1462KVE33

Description

36-Mbit (1M x 36/2M x 18) Pipelined SRAM



Feature


CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With EC C) 36-Mbit (1M × 36/2M × 18) Pipelin ed SRAM with NoBL™ Architecture (With ECC) Features ■ Pin-compatible and f unctionally equivalent to Zero Bus Turn around (ZBT™) ■ Supports 250-MHz bu s operations with zero wait states ❐ Available speed grades are 250, 20.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1462KVE33 Datasheet


Cypress Semiconductor CY7C1462KVE33

CY7C1462KVE33; 0, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully- registered (inputs and outputs) for pip elined operation ■ Byte write capabil ity ■ 3.3-V power supply ■ 3.3-V/2. 5-V I/O power supply ■ Fast clock-to- output time ❐ 2.5 ns (for 250-MHz dev ice) ■ Clock enable (CEN) pin to susp end operation ■ Synchronous self-t.


Cypress Semiconductor CY7C1462KVE33

imed writes ■ CY7C1460KV33, CY7C1460KV E33, CY7C1462KVE33 available in JEDEC-s tandard Pb-free 100-pin TQFP, Pb-free a nd non Pb-free 165-ball FBGA packages IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability—l .


Cypress Semiconductor CY7C1462KVE33

.





Part

CY7C1462KVE33

Description

36-Mbit (1M x 36/2M x 18) Pipelined SRAM



Feature


CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With EC C) 36-Mbit (1M × 36/2M × 18) Pipelin ed SRAM with NoBL™ Architecture (With ECC) Features ■ Pin-compatible and f unctionally equivalent to Zero Bus Turn around (ZBT™) ■ Supports 250-MHz bu s operations with zero wait states ❐ Available speed grades are 250, 20.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1462KVE33 Datasheet




 CY7C1462KVE33
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to Zero Bus
Turnaround (ZBT™)
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully-registered (inputs and outputs) for pipelined operation
Byte write capability
3.3-V power supply
3.3-V/2.5-V I/O power supply
Fast clock-to-output time
2.5 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 165-ball FBGA packages
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability—linear or interleaved burst order
“ZZ” sleep mode option
On-chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. 6
This feature dramatically improves the throughput of data in
systems that require frequent write and read transitions. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460KV33/CY7C1460KVE33 and
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) enable easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
250 MHz 200 MHz 167 MHz Unit
2.5 3.2 3.4 ns
× 18 220 190 170 mA
× 36 240 210 190
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66680 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2016




 CY7C1462KVE33
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Logic Block Diagram – CY7C1460KV33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1460KVE33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWA
BWB
BWC
BWD
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
ECC
ENCODER
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
E
C
C
D
E
C
O
D
E
R
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPA
DQPB
DQPC
DQPD
READ LOGIC
SLEEP
CONTROL
Document Number: 001-66680 Rev. *K
Page 2 of 31




 CY7C1462KVE33
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Logic Block Diagram – CY7C1462KVE33
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1 Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
O
U
T
S
E
N
P
U
T
D
A
T
O
U
T
EP
CU
CT
WRITE
DRIVERS
MEMORY
ARRAY
S
E
A
M
P
S
R
E
G
I
S
T
E
R
S
A
S
T
E
E
R
I
N
G
D
E
C
O
D
E
R
B
U
F
F
E
R
S
EE
DQs
DQPA
DQPB
ECC
ENCODER
INPUT
REGISTER1 E
INPUT
REGISTER0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ
Sleep
Control
Document Number: 001-66680 Rev. *K
Page 3 of 31




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