Dual-Port RAM. CY7C0853AV Datasheet

CY7C0853AV RAM. Datasheet pdf. Equivalent

CY7C0853AV Datasheet
Recommendation CY7C0853AV Datasheet
Part CY7C0853AV
Description 3.3 V 32 K / 64 K / 128 K / 256 K x 36 Synchronous Dual-Port RAM
Feature CY7C0853AV; CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV FLEx36™ 3.3 V 32 K / 64 K / 128 K / 2.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C0853AV Datasheet




Cypress Semiconductor CY7C0853AV
FLEx36™ 3.3 V, 32K/64K/128K/256K × 36 Synchronous Dual-Port RAM
Features
True dual-ported memory cells that allow simultaneous access
of the same memory location
Synchronous pipelined operation
Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
Pipelined output mode allows fast operation
0.18-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed and power
High-speed clock to data access
3.3 V low power
Active as low as 225 mA (typ)
Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible Joint test action group (JTAG)
boundary scan
172-ball fine-pitch ball grid array (FBGA) (1 mm pitch)
(15 mm × 15 mm)
176-pin thin quad plastic flatpack (TQFP)
(24 mm × 24 mm × 1.4 mm)
Counter wrap around control
Internal mask register controls counter wrap-around
Counter-interrupt flags to indicate wrap-around
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual chip enables on both ports for easy depth expansion
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
FLEx36™ 3.3 V,
32K/64K/128K/256K × 36
Synchronous Dual-Port RAM
Functional Description
The FLEx36™ family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
For a complete list of related documentation, click here.
Product Selection Guide
Density
2-Mbit (64K × 36)
4-Mbit (128K × 36)
Part number
CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV
Max. speed (MHz)
167 167
Max. access time - clock to data (ns)
4.0
4.0
Typical operating current (mA)
225
225
Package
176-pin TQFP, 172-ball FBGA 176-pin TQFP, 172-ball FBGA
9-Mbit (256K × 36)
CY7C0853V/CY7C0853AV
133
4.7
270
172-ball FBGA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06070 Rev. *R
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 12, 2019



Cypress Semiconductor CY7C0853AV
Logic Block Diagram
The Logic Block Diagram is as follows. [1]
OEL
R/WL
B0L
B1L
B2L
B3L
CE0L
CE1L
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
OER
R/WR
B0R
B1R
B2R
B3R
CE0R
CE1R
DQ27L–DQ35L
DQ18L–DQ26L
DQ9L–DQ17L
DQ0L–DQ8L
9
9
9
9
I/O
Control
I/O
Control
9 DQ27R–DQ35R
9 DQ18R–DQ26R
9 DQ9R–DQ17R
9 DQ0R–DQ8R
Addr.
Read
Back
A0L–A17L
CNT/MSKL
18
Mask Register
True
Dual-Ported
RAM Array
Addr.
Read
Back
Mask Register
ADSL
CNTENL
CNTRSTL
CLKL
CNTINTL
INTL
Counter/
Address
Register
Mirror Reg
Address
Decode
Address
Decode
Interrupt
Logic
MRST
Reset
Logic
TMS
TDI
TCK
JTAG
Counter/
Address
Register
Mirror Reg
TDO
Interrupt
Logic
Note
1. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.
18 A0R–A17R
CNT/MSKR
ADS
CNTEN
CNTRSTR
CLKR
CNTINTR
INTR
Document Number: 38-06070 Rev. *R
Page 2 of 38



Cypress Semiconductor CY7C0853AV
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Master Reset ............................................................... 8
Mailbox Interrupts ........................................................ 8
Read/Write and Enable Operation (Any Port) ............. 8
Address Counter and Mask Register Operations ........ 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Performing a TAP Reset ........................................... 13
Performing a Pause/Restart ...................................... 13
Identification Register Definitions ................................ 13
Scan Registers Sizes ..................................................... 13
Instruction Identification Codes .................................... 13
Maximum Ratings ........................................................... 14
Operating Range ............................................................. 14
Electrical Characteristics ............................................... 14
Capacitance .................................................................... 15
AC Test Load and Waveforms ....................................... 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 18
JTAG Timing ................................................................... 29
Ordering Information ...................................................... 30
256K × 36 (9M) 3.3 V Synchronous
CY7C0853V/CY7C0853AV Dual-Port SRAM ................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC® Solutions ...................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Document Number: 38-06070 Rev. *R
Page 3 of 38







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