Static RAM. CY7C09159AV Datasheet

CY7C09159AV RAM. Datasheet pdf. Equivalent

CY7C09159AV Datasheet
Recommendation CY7C09159AV Datasheet
Part CY7C09159AV
Description 3.3-V 8 K x 9 Synchronous Dual Port Static RAM
Feature CY7C09159AV; CY7C09169AVTITLE CY7C09159AV 3.3-V 8 K × 9 Synchronous Dual Port Static RAM Features ■ True dual-p.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C09159AV Datasheet




Cypress Semiconductor CY7C09159AV
CY7C09169AVTITLE
CY7C09159AV
3.3-V 8 K × 9
Synchronous Dual Port Static RAM
Features
True dual-ported memory cells which allow simultaneous
access of the same memory location
Flow-through/Pipelined device
8 K × 9 organization (CY7C09159AV)
Three Modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports allows fast 67-MHz
operation
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed clock to data access 9 ns (max.)
Logic Block Diagram
3.3 V Low operating power
Active = 135 mA (typical)
Standby = 10 A (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in Flow-through and Pipelined modes
Dual chip enables for easy depth expansion
Automatic power-down
Commercial temperature ranges
Available in 100-pin thin quad plastic flatpack (TQFP)
Pb-free packages available
For a complete list of related documentation, click here.
R/WL
OEL
R/WR
OER
CE0L
CE1L
1
0
0/1
1 CE0R
0 CE1R
0/1
FT/PipeL
I/O0LI/O8L
10
0/1
9
A0A12L
CLKL
ADSL
CNTENL
CNTRSTL
13
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
01
0/1
9
FT/PipeR
I/O0RI/O8R
Counter/
Address
Register
Decode
13
A0A12R
CLKR
ADSR
CNTENR
CNTRSTR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06053 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014



Cypress Semiconductor CY7C09159AV
CY7C09159AV
Functional Description
The CY7C09159AV is a high-speed synchronous CMOS 8 K × 9
dual-port static RAM. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory.[1] Registers on control, address, and data
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid tCD2 = 9 ns (pipelined). Flow-through mode can also be
used to bypass the pipelined output register to eliminate access
latency. In flow-through mode data will be available tCD1 = 20 ns
after the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW- to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations. In
the pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin thin quad plastic flatpack
(TQFP) packages.
Note
1. When simultaneously writing to the same location, final value cannot be guaranteed.
Document Number: 38-06053 Rev. *F
Page 2 of 19



Cypress Semiconductor CY7C09159AV
CY7C09159AV
Contents
Pin Configuration ............................................................. 4
100-Pin TQFP (Top View) ................................................. 4
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 5
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics
Over the Operating Range ............................................... 6
Capacitance ...................................................................... 6
AC Test Loads .................................................................. 6
Switching Characteristics
Over the Operating Range ............................................... 7
Switching Waveforms ...................................................... 8
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Document Number: 38-06053 Rev. *F
Page 3 of 19







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