Static RAM. CY7C09279V Datasheet

CY7C09279V RAM. Datasheet pdf. Equivalent

CY7C09279V Datasheet
Recommendation CY7C09279V Datasheet
Part CY7C09279V
Description 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
Feature CY7C09279V; CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C09279V Datasheet




Cypress Semiconductor CY7C09279V
CY7C09269V/79V/89V
CY7C09369V/89V
3.3 V 16K / 32K / 64K × 16 / 18
Synchronous Dual-Port Static RAM
3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM
Features
True dual-ported memory cells that allow simultaneous access
of the same memory location
Six flow through/pipelined devices:
16K × 16 / 18 organization (CY7C09269V/369V)
32K × 16 organization (CY7C09279V)
64K × 16 / 18 organization (CY7C09289V/389V)
Three modes:
Flow through
Pipelined
Burst
Pipelined output mode on both ports allows fast 100 MHz
operation
0.35 micron CMOS for optimum speed and power
High speed clock to data access: 7.5[1], 9, 12 ns (max)
3.3 V low operating power:
Logic Block Diagram
R/WL
UBL
Active = 115 mA (typical)
Standby = 10 A (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
Shorten cycle times
Minimize bus noise
Supported in flow through and pipelined modes
Dual chip enables easy depth expansion
Upper and lower byte controls for bus matching
Automatic power down
Commercial and industrial temperature ranges
Pb-free 100-pin TQFP package available
Functional Description
For a complete list of related documentation, click here.
R/WR
UBR
CE0L
CE1L
LBL
OEL
1
0
0/1
1 CE0R
0 CE1R
0/1 LBR
OER
FT/PipeL
[2]
I/O8/9L–I/O15/17L
1b 0b 1a 0a
0/1 b
a
8/9
[3]
I/O0L–I/O7/8L
8/9
[4] 14/15/16
A0L–A13/14/15L
CLKL
ADSL
Counter/
Address
Register
CNTENL
Decode
CNTRSTL
Notes
1. See Figure 4 on page 8 for Load Conditions.
2. I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices.
3. I/O0–I/O7 for × 16 devices. I/O0–I/O8 for × 18 devices.
4. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0a 1a 0b 1b
a b 0/1
8/9
FT/PipeR
[2]
I/O8/9R–I/O15/17R
Counter/
Address
Register
Decode
8/9 [3]
I/O0R–I/O7/8R
14/15/16
[4]
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06056 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 21, 2016



Cypress Semiconductor CY7C09279V
CY7C09269V/79V/89V
CY7C09369V/89V
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 5
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 10
Read/Write and Enable Operation ................................. 18
Address Counter Control Operation ............................. 18
Ordering Information ...................................................... 19
16K × 16 3.3 V Synchronous Dual-Port SRAM ......... 19
32K × 16 3.3 V Synchronous Dual-Port SRAM ......... 19
16K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19
64K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 38-06056 Rev. *M
Page 2 of 25



Cypress Semiconductor CY7C09279V
Pin Configurations
CY7C09269V/79V/89V
CY7C09369V/89V
Figure 1. 100-pin TQFP pinout (Top View)
A9L
A10L
A11L
A12L
A13L
[5] A14L
[6] A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
FT/PIPEL
[7] GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 66
11 CY7C09289V (64K × 16) 65
12 64
13 CY7C09279V (32K × 16) 63
14 62
15 CY7C09269V (16K × 16) 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R
A10R
A11R
A12R
A13R
A14R [5]
A15R [6]
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND [7]
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
Notes
5. This pin is NC for CY7C09269V.
6. This pin is NC for CY7C09269V and CY7C09279V.
7. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5 V × 16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5 V × 16 flow through device.
Document Number: 38-06056 Rev. *M
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