Static RAM. CY7C09349AV Datasheet

CY7C09349AV RAM. Datasheet pdf. Equivalent

CY7C09349AV Datasheet
Recommendation CY7C09349AV Datasheet
Part CY7C09349AV
Description 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM
Feature CY7C09349AV; CY7C09359AV3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM CY7C09349AV CY7C09359AV 3.3 V 4 K/8 .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C09349AV Datasheet




Cypress Semiconductor CY7C09349AV
CY7C09359AV3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
CY7C09349AV
CY7C09359AV
3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM
Features
True dual ported memory cells which allow simultaneous
access of the same memory location
Two flow-through/pipelined devices
4 K × 18 organization (CY7C09349AV)
8 K × 18 organization (CY7C09359AV)
Three modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports allows fast 67-MHz
operation
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
Logic Block Diagram
R/WL
UBL
High-speed clock to data access 9 and 12 ns (max)
3.3 V low operating power
Active = 135 mA (typical)
Standby = 10 µA (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in flow-through and pipelined modes
Dual chip enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Available in 100-pin thin quad flat pack (TQFP)
For a complete list of related documentation, click here.
R/WR
UBR
CE0L
CE1L
LBL
OEL
1
0
0/1
1 CE0R
0 CE1R
0/1 LBR
OER
FT/PipeL
I/O9L–I/O17L
I/O0L–I/O8L
[1]
A0L–A11/12L
CLKL
ADSL
CNTENL
CNTRSTL
1b 0b 1a 0a
0/1 b
a
9
9
12/13
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual Ported
RAM Array
0a 1a 0b 1b
a b 0/1
9
FT/PipeR
I/O9R–I/O17R
Counter/
Address
Register
Decode
9
12/13
I/O0R–I/O8R
[1]
A0R–A11/12R
CLKR
ADSR
CNTENR
CNTRSTR
Note
1. A0–A11 for 4 K; A0–A12 for 8 K devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-63888 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 26, 2014



Cypress Semiconductor CY7C09349AV
CY7C09349AV
CY7C09359AV
Functional Description
The CY7C09349AV and CY7C09359AV are high-speed 3.3 V
synchronous CMOS 4 K and 8 K × 18 dual-port static RAMs. Two
ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.[2]
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
tCD2 = 9 ns (pipelined). Flow-through mode can also be used to
bypass the pipelined output register to eliminate access latency.
In flow-through mode data will be available tCD1 = 20 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple chip enables allows easier
banking of multiple chips for depth expansion configurations. In
the pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s address strobe
(ADS). When the port’s count enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin thin quad plastic flatpack
(TQFP) packages.
Note
2. When simultaneously writing to the same location, final value cannot be guaranteed.
Document Number: 001-63888 Rev. *C
Page 2 of 20



Cypress Semiconductor CY7C09349AV
CY7C09349AV
CY7C09359AV
Contents
Pin Configuration ............................................................. 4
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 5
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 6
AC Test Loads .................................................................. 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Address Counter Control Operation[31, 35, 36, 37] .......... 15
Read/Write and Enable Operation[31, 32, 33] .................. 15
Ordering Information ...................................................... 16
4 K × 18 3.3 V Synchronous Dual-Port SRAM .......... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Document Number: 001-63888 Rev. *C
Page 3 of 20







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)