Sync SRAM. CY7C1444AV33 Datasheet

CY7C1444AV33 SRAM. Datasheet pdf. Equivalent

CY7C1444AV33 Datasheet
Recommendation CY7C1444AV33 Datasheet
Part CY7C1444AV33
Description 36-Mbit Pipelined DCD Sync SRAM
Feature CY7C1444AV33; CY7C1444AV33 36-Mbit (1M × 36) Pipelined DCD Sync SRAM 36-Mbit (1M × 36) Pipelined DCD Sync SRAM Fe.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1444AV33 Datasheet





Cypress Semiconductor CY7C1444AV33
CY7C1444AV33
36-Mbit (1M × 36) Pipelined DCD Sync
SRAM
36-Mbit (1M × 36) Pipelined DCD Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades are 250 MHz and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3 V core power supply
2.5 V/3.3 V I/O power supply
Fast clock-to-output times
2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1444AV33 available in JEDEC-standard Pb-free 100-pin
TQFP package
“ZZ” sleep mode option
Functional Description
The CY7C1444AV33 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444AV33 operates from a +3.3 V core power supply
while all outputs operate with a +3.3 V or a +2.5 V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.6
475
120
167 MHz
3.4
375
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05352 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 2, 2016



Cypress Semiconductor CY7C1444AV33
CY7C1444AV33
Logic Block Diagram – CY7C1444AV33
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQD,DQPD
BYTE
WRITE REGISTER
DQc,DQPC
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE REGISTER
DQA,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD,DQPD
BYTE
WRITE DRIVER
DQc,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
OUTPUT
SENSE
AMPS
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 38-05352 Rev. *N
Page 2 of 24



Cypress Semiconductor CY7C1444AV33
CY7C1444AV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC Solutions ......................................................... 24
Document Number: 38-05352 Rev. *N
Page 3 of 24





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