Sync SRAM. CY7C1446AV25 Datasheet

CY7C1446AV25 SRAM. Datasheet pdf. Equivalent

CY7C1446AV25 Datasheet
Recommendation CY7C1446AV25 Datasheet
Part CY7C1446AV25
Description 36-Mbit Pipelined Sync SRAM
Feature CY7C1446AV25; CY7C1440AV25 CY7C1446AV25 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM 36-Mbit (1 M × 36/512 K.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1446AV25 Datasheet





Cypress Semiconductor CY7C1446AV25
CY7C1440AV25
CY7C1446AV25
36-Mbit (1 M × 36/512 K × 72)
Pipelined Sync SRAM
36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades are 250 and 167 MHz
Registered inputs and outputs for pipelined operation
2.5 V core power supply
2.5 V power supply
Fast clock-to-output times
2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single-cycle Chip Deselect
CY7C1440AV25 available in Pb-free and non-Pb-free 165-ball
FBGA package. CY7C1446AV25 available in non-Pb-free
209-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
The CY7C1440AV25/CY7C1446AV25 SRAM integrates
1 M × 36/512 K × 72 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440AV25/CY7C1446AV25 operates from a +2.5 V
core power supply while all outputs may operate with a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
250 MHz
2.6
435
120
167 MHz
3.4
335
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70167 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 5, 2016



Cypress Semiconductor CY7C1446AV25
CY7C1440AV25
CY7C1446AV25
Logic Block Diagram – CY7C1440AV25
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD ,DQPD
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
ZZ SLEEP
CONTROL
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
Document Number: 001-70167 Rev. *E
Page 2 of 33



Cypress Semiconductor CY7C1446AV25
CY7C1440AV25
CY7C1446AV25
Logic Block Diagram – CY7C1446AV25
A0, A1,A
MODE
ADV
CLK
ADSC
ADSP
ADDRESS
REGISTER
A[1:0]
Q1
BINARY
COUNTER
CLR Q0
BWH
BWG
BWF
BWE
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
DQH, DQPH
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
ZZ CONTROL
DQH, DQPH
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DBQYET,ED“QaP”E
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
Document Number: 001-70167 Rev. *E
Page 3 of 33





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