Flow-Through SRAM. CY7C1447AV25 Datasheet

CY7C1447AV25 SRAM. Datasheet pdf. Equivalent

CY7C1447AV25 Datasheet
Recommendation CY7C1447AV25 Datasheet
Part CY7C1447AV25
Description 36-Mbit Flow-Through SRAM
Feature CY7C1447AV25; Not Recommended for New Designs. CY7C1441AV25 CY7C1447AV25 36-Mbit (1M × 36/512K × 72) Flow-Through.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1447AV25 Datasheet





Cypress Semiconductor CY7C1447AV25
CY7C1441AV25
CY7C1447AV25
36-Mbit (1M × 36/512K × 72)
Flow-Through SRAM
36-Mbit (1M × 36/512K × 72) Flow-Through SRAM
Features
Supports 133 MHz bus operations
1M × 36/512K × 72 common I/O
2.5 V core power supply
2.5 V I/O power supply
Fast clock-to-output times
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
CY7C1441AV25 available in Pb-free 165-ball FBGA package.
CY7C1447AV25 available in non Pb-free 209-ball FBGA
package.
JTAG boundary scan for FBGA package
ZZ sleep mode option
Functional Description
The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1M × 36/512K × 72
Synchronous Flow-Through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address pipelining Chip Enable (CE1), depth expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV25/CY7C1447AV25 allows either interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence and a LOW selects
a linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either ADSP or ADSC are active. Subsequent burst
addresses can be internally generated as controlled by the ADV.
The CY7C1441AV25/CY7C1447AV25 operates from a
+2.5 V core power supply while all outputs may operate with
either a +2.5 V supply. All inputs and outputs are
JEDEC-standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
270
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75380 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 7, 2016



Cypress Semiconductor CY7C1447AV25
Logic Block Diagram – CY7C1441AV25
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A [1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
CY7C1441AV25
CY7C1447AV25
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
Document Number: 001-75380 Rev. *F
Page 2 of 33



Cypress Semiconductor CY7C1447AV25
CY7C1441AV25
CY7C1447AV25
Logic Block Diagram – CY7C1447AV25
A0, A1,A
MODE
ADV
CLK
ADSC
ADSP
BW H
BW G
BW F
BW E
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ H, DQPH
WRITE REGISTER
DQ F, DQPF
WRITE REGISTER
DQ F, DQPF
WRITE REGISTER
DQ E, DQPE
WRITE REGISTER
DQ D, DQPD
WRITE REGISTER
DQ C, DQPC
WRITE REGISTER
DQ B, DQPB
WRITE REGISTER
DQ A, DQPA
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQ H, DQPH
WRITE DRIVER
DQ G, DQPG
WRITE DRIVER
DQ F, DQPF
WRITE DRIVER
DBQYTEE, D“Qa”PE
WRITE DRIVER
DQ D, DQPD
WRITE DRIVER
DQ C, DQPC
WRITE DRIVER
DQ B, DQPB
WRITE DRIVER
DQ A, DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
Document Number: 001-75380 Rev. *F
Page 3 of 33





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