CY7C1418KV18/CY7C1420KV18
36-Mbit DDR II SRAM Two-Word Burst Architecture
36-Mbit DDR II SRAM Two-Word Burst Architecture
Features
■ 36-Mbit density (2M × 18, 1M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz ■ Two input clocks (K and K...