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CY7C1521KV18

Part Number	CY7C1521KV18
Manufacturer	Cypress Semiconductor
Description	72-Mbit DDR II SRAM Four-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture Features...
Datasheet	CY7C1521KV18 PDF File

Overview

CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 72-Mbit Density (2M × 36) ■ 250 MHz Clock for High Bandwidth ■ Four-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces (data transferred at 500 MHz) at 250 MHz ■ Two Input Clocks (K and K) for precise DDR Timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches ■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems ■ Synchronous Internally Self-timed Writes ■ DDR II operates with 1.
5 Cycle Read Latency when DOFF is asserted HIGH ■ Operates similar to D...

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CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture - Cypress Semiconductor

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