Burst Architecture. CY7C1521KV18 Datasheet

CY7C1521KV18 Architecture. Datasheet pdf. Equivalent

CY7C1521KV18 Datasheet
Recommendation CY7C1521KV18 Datasheet
Part CY7C1521KV18
Description 72-Mbit DDR II SRAM Four-Word Burst Architecture
Feature CY7C1521KV18; CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst A.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1521KV18 Datasheet





Cypress Semiconductor CY7C1521KV18
CY7C1521KV18
72-Mbit DDR II SRAM Four-Word
Burst Architecture
72-Mbit DDR II SRAM Four-Word Burst Architecture
Features
72-Mbit Density (2M × 36)
250 MHz Clock for High Bandwidth
Four-word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces (data transferred at
500 MHz) at 250 MHz
Two Input Clocks (K and K) for precise DDR Timing
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Synchronous Internally Self-timed Writes
DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
1.8V Core Power Supply with HSTL Inputs and Outputs
Variable drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4 V–VDD)
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
Offered in Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase Locked Loop (PLL) for accurate Data Placement
Configurations
CY7C1521KV18 – 2M × 36
Functional Description
The CY7C1521KV18 is 1.8 V Synchronous Pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. For CY7C1521KV18 the
burst counter takes in the least two significant bits of the external
address and bursts four 36-bit words in the case of
CY7C1521KV18, sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
250 MHz Unit
250 MHz
× 36 420 mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00439 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2016



Cypress Semiconductor CY7C1521KV18
CY7C1521KV18
Logic Block Diagram – CY7C1521KV18
A(1:0)
2
Burst
Logic
A(20:0)
21 19
A(20:2)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[3:0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
36
Read Data Reg.
144
72
72
Output
Logic
Control
R/W
C
C
Reg.
Reg.
36
Reg. 36
36
36
36
CQ
CQ
DQ[35:0]
Document Number: 001-00439 Rev. *L
Page 2 of 29



Cypress Semiconductor CY7C1521KV18
CY7C1521KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
PLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Burst Address Table ........................................................ 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in DDR II SRAM ........................... 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagram ............................................................ 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 001-00439 Rev. *L
Page 3 of 29





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