Burst Architecture. CY7C1620KV18 Datasheet

CY7C1620KV18 Architecture. Datasheet pdf. Equivalent

CY7C1620KV18 Datasheet
Recommendation CY7C1620KV18 Datasheet
Part CY7C1620KV18
Description 144-Mbit DDR II SRAM Two-Word Burst Architecture
Feature CY7C1620KV18; CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1620KV18 Datasheet




Cypress Semiconductor CY7C1620KV18
CY7C1618KV18/CY7C1620KV18
144-Mbit DDR II SRAM Two-Word
Burst Architecture
144-Mbit DDR II SRAM Two-Word Burst Architecture
Features
144-Mbit density (8M × 18, 4M × 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5-cycle read latency when DOFF is
asserted high
Operates similar to DDR I device with one cycle read latency
when DOFF is asserted low
1.8-V core power supply with high-speed transceiver logic
(HSTL) inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–VDD)
Supports both 1.5-V and 1.8-V I/O supply
Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configuration
CY7C1618KV18 – 8M × 18
CY7C1620KV18 – 4M × 36
Functional Description
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1618KV18 and CY7C1620KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1618KV18 and two 36-bit words in the case of
CY7C1620KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz Unit
333 300 250 MHz
× 18 650
610 Not Offered mA
× 36 790 Not Offered 660
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44274 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 9, 2016



Cypress Semiconductor CY7C1620KV18
CY7C1618KV18/CY7C1620KV18
Logic Block Diagram – CY7C1618KV18
Burst
A0 Logic
A(22:0)
23 22
A(22:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[1:0]
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36
18
18
18
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ[17:0]
Logic Block Diagram – CY7C1620KV18
A0
Burst
Logic
A(21:0)
22 21
A(21:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[3:0]
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
36
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ[35:0]
Document Number: 001-44274 Rev. *M
Page 2 of 32



Cypress Semiconductor CY7C1620KV18
CY7C1618KV18/CY7C1620KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Single Clock Mode ...................................................... 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Burst Address Table ........................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in DDR II SRAM ........................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ........................................ 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 26
Read/Write/Deselect Sequence ................................ 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions and Legal Information ....................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-44274 Rev. *M
Page 3 of 32





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