Burst Architecture. CY7C2562XV18 Datasheet

CY7C2562XV18 Architecture. Datasheet pdf. Equivalent

CY7C2562XV18 Datasheet
Recommendation CY7C2562XV18 Datasheet
Part CY7C2562XV18
Description 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Feature CY7C2562XV18; .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C2562XV18 Datasheet




Cypress Semiconductor CY7C2562XV18
CY7C2562XV18/CY7C2564XV18
72-Mbit QDR® II+ Xtreme SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Separate independent read and write data ports
Supports concurrent transactions
450 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V ± 0.1 V; VDDQ = 1.4 V to 1.6 V
Supports 1.5 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
CY7C2564XV18 offered in both Pb-free and non Pb-free
packages and CY7C2562XV18 offered in Pb-free package
only.
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2562XV18 – 4M × 18
CY7C2564XV18 – 2M × 36
Functional Description
The CY7C2562XV18 and CY7C2564XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR™-II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common devices. Access to each port is through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 18-bit words
(CY7C2562XV18), or 36-bit words (CY7C2564XV18) that burst
sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
These devices have an on-die termination (ODT) feature
supported
eliminate
efxotrernDa[xl:0t]e, rmBWinaSt[ixo:0n],
and K/K
resistors,
inputs,
reduce
which helps
cost, reduce
board area, and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
450 MHz 366 MHz Unit
450 366 MHz
× 18 1205
970 mA
× 36 1445
1165
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70204 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 12, 2016



Cypress Semiconductor CY7C2562XV18
CY7C2562XV18/CY7C2564XV18
Logic Block Diagram – CY7C2562XV18
D[17:0]
18
A(20:0) 21
Address
Register
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
21 A(20:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
Q[17:0]
QVLD
Logic Block Diagram – CY7C2564XV18
D[35:0]
36
A(19:0) 20
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Address
Register
20 A(19:0)
Control
Logic
RPS
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-70204 Rev. *F
Page 2 of 29



Cypress Semiconductor CY7C2562XV18
CY7C2562XV18/CY7C2564XV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
On-Die Termination (ODT) .......................................... 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in QDR II+ Xtreme SRAM ............ 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Read/Write/Deselect Sequence ................................ 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagram ............................................................ 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 001-70204 Rev. *F
Page 3 of 29





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