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CY7C1168KV18
18-Mbit DDR II+ SRAM Two-Word Burst Architecture
Description
CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ 18-Mbit density (1M × 18, 512K × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transfer...
Cypress Semiconductor
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CY7C1168KV18
18-Mbit DDR II+ SRAM Two-Word Burst Architecture
- Cypress Semiconductor
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