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CY7C1548KV18
72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Description
CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ 72-Mbit density (4M × 18, 2M × 36) ■ 450-MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred ...
Cypress Semiconductor
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CY7C1548KV18
72-Mbit DDR II+ SRAM Two-Word Burst Architecture
- Cypress Semiconductor
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