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Static RAM. CY62177EV18 Datasheet

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Static RAM. CY62177EV18 Datasheet






CY62177EV18 RAM. Datasheet pdf. Equivalent




CY62177EV18 RAM. Datasheet pdf. Equivalent





Part

CY62177EV18

Description

32-Mbit (2 M x 16 / 4 M x 8) Static RAM



Feature


CY62177EV18 MoBL® 32-Mbit (2 M × 16 / 4 M × 8) Static RAM 32-Mbit (2 M × 1 6 / 4 M × 8) Static RAM Features ■ T hin small outline package (TSOP) I conf igurable as 2 M × 16 or as 4 M × 8 st atic RAM (SRAM) ■ Very high speed ❐ 70 ns ■ Wide voltage range ❐ 1.65 V to 2.25 V ■ Ultra low standby power ❐ Typical standby current: 3 A Maximum standby current: 25 A ■ Ultra lo.
Manufacture

Cypress Semiconductor

Datasheet
Download CY62177EV18 Datasheet


Cypress Semiconductor CY62177EV18

CY62177EV18; w active power ❐ Typical active curren t: 4.5 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE Feature s ■ Automatic power-down when deselec ted ■ Complementary metal oxide semic onductor (CMOS) for optimum speed and p ower ■ Available in Pb-free 48-ball T SOP I and 48-ball FBGA package Functio nal Description The CY62177EV18 is a hi gh-performance CMOS static R.


Cypress Semiconductor CY62177EV18

AM organized as 2 M words by 16 bits and 4 M words by 8 bits. This device featu res advanced circuit design to provide ultra low active current. It is ideal f or providing More Battery Life (MoBL ®) in portable applicati .


Cypress Semiconductor CY62177EV18

.

Part

CY62177EV18

Description

32-Mbit (2 M x 16 / 4 M x 8) Static RAM



Feature


CY62177EV18 MoBL® 32-Mbit (2 M × 16 / 4 M × 8) Static RAM 32-Mbit (2 M × 1 6 / 4 M × 8) Static RAM Features ■ T hin small outline package (TSOP) I conf igurable as 2 M × 16 or as 4 M × 8 st atic RAM (SRAM) ■ Very high speed ❐ 70 ns ■ Wide voltage range ❐ 1.65 V to 2.25 V ■ Ultra low standby power ❐ Typical standby current: 3 A Maximum standby current: 25 A ■ Ultra lo.
Manufacture

Cypress Semiconductor

Datasheet
Download CY62177EV18 Datasheet




 CY62177EV18
CY62177EV18 MoBL®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M × 8 static RAM (SRAM)
Very high speed
70 ns
Wide voltage range
1.65 V to 2.25 V
Ultra low standby power
Typical standby current: 3 A
Maximum standby current: 25 A
Ultra low active power
Typical active current: 4.5 mA at f = 1 MHz
Easy memory expansion with CE1, CE2, and OE Features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 48-ball TSOP I and 48-ball FBGA package
Functional Description
The CY62177EV18 is a high-performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications, such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
2M × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power-Down
Circuit
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-76091 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 28, 2014




 CY62177EV18
CY62177EV18 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-76091 Rev. *C
Page 2 of 17




 CY62177EV18
CY62177EV18 MoBL®
Pin Configuration
Figure 1. 48-pin TSOP I pinout (Front View) [1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 Vss
45 I/O15/A21
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 Vcc
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 Vss
26 CE1
25 A0
Figure 2. 48-ball FBGA pinout (Top View)
12
34
56
BLE OE A0 A1 A2 CE2
I/O8 BHE A3 A4 CE1 I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 Vcc
VCC I/O12 NC
A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 A19 A12 A13 WE I/O7
A18 A8 A9 A10 A11 A20
A
B
C
D
E
F
G
H
Product Portfolio
Product
CY62177EV18LL
VCC Range (V)
Min
1.65
Typ[3]
1.8
Max
2.25
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1 MHz
Typ[3]
Max
f = fMax
Typ[3]
Max
Standby ISB2 (A)
Typ[3]
Max
4.5 5.5 35 45
3
25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 4 M × 8
SRAM by tying the BYTE signal to VSS. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-76091 Rev. *C
Page 3 of 17






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