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Static RAM. CY7C1069GE Datasheet

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Static RAM. CY7C1069GE Datasheet






CY7C1069GE RAM. Datasheet pdf. Equivalent




CY7C1069GE RAM. Datasheet pdf. Equivalent





Part

CY7C1069GE

Description

16-Mbit (2M words x 8 bit) Static RAM



Feature


CY7C1069G CY7C1069GE 16-Mbit (2M words 8 bit) Static RAM with Error-Correcti ng Code (ECC) 16-Mbit (2M words × 8 b it) Static RAM with Error-Correcting Co de (ECC) Features ■ High speed ❐ tA A = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correc tion ■ Low active and standby current s ❐ ICC = 90 mA typical at 100 MHz ISB2 = 20 mA typical ■ Operati.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1069GE Datasheet


Cypress Semiconductor CY7C1069GE

CY7C1069GE; ng voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V ■ 1.0-V dat a retention ■ Transistor-transistor l ogic (TTL) compatible inputs and output s ■ ERR pin to indicate 1-bit error d etection and correction ■ Available i n Pb-free 54-pin TSOP II, and 48-ball V FBGA packages Functional Description Th e CY7C1069G and CY7C1069GE are dual chi p enable high-performance .


Cypress Semiconductor CY7C1069GE

CMOS fast static RAM devices with embedd ed ECC. The CY7C1069G device is availab le in standard pin configurations. The CY7C1069GE device includes a single bit error indication pin (ERR) that signal s the host processor in the case of an .


Cypress Semiconductor CY7C1069GE

.

Part

CY7C1069GE

Description

16-Mbit (2M words x 8 bit) Static RAM



Feature


CY7C1069G CY7C1069GE 16-Mbit (2M words 8 bit) Static RAM with Error-Correcti ng Code (ECC) 16-Mbit (2M words × 8 b it) Static RAM with Error-Correcting Co de (ECC) Features ■ High speed ❐ tA A = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correc tion ■ Low active and standby current s ❐ ICC = 90 mA typical at 100 MHz ISB2 = 20 mA typical ■ Operati.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1069GE Datasheet




 CY7C1069GE
CY7C1069G
CY7C1069GE
16-Mbit (2M words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
High speed
tAA = 10 ns
Embedded error-correcting code (ECC) for single-bit error
correction
Low active and standby currents
ICC = 90 mA typical at 100 MHz
ISB2 = 20 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V
to 5.5 V
1.0-V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
ERR pin to indicate 1-bit error detection and correction
Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
The CY7C1069G and CY7C1069GE are dual chip enable
high-performance CMOS fast static RAM devices with
embedded ECC. The CY7C1069G device is available in
standard pin configurations. The CY7C1069GE device includes
a single bit error indication pin (ERR) that signals the host
processor in the case of an ECC error-detection and correction
event.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A20).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table – CY7C1069G/CY7C1069GE on page
14 for a complete description of Read and Write modes. The
input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH, and WE LOW).
On CY7C1069GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High) [1].
All I/Os (I/O0 through I/O7) are placed in a high impedance state
when the device is deselected (CE1 HIGH or CE2 LOW), and
control signals are de-asserted (CE1 / CE2, OE, WE).
CY7C1069G and CY7C1069GE devices are available in a
54-pin TSOP II package with center power and ground
(revolutionary) pinout, and in a 48-ball VFBGA package.
For a complete list of related documentation, here.
Note
1. Automatic write back on error detection feature is not supported in this device.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-81539 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 5, 2017




 CY7C1069GE
Logic Block Diagram – CY7C1069G
ECC ENCODER
DATAIN 
DRIVERS
A0
A1
A2
A3
A4
A5
2M x 8
RAM ARRAY
A6
A7
A8
A9
COLUMN 
DECODER
Logic Block Diagram – CY7C1069GE
ECC ENCODER
DATAIN 
DRIVERS
A0
A1
A2
A3
A4
2M x 8
A5 RAM ARRAY
A6
A7
A8
A9
COLUMN 
DECODER
CY7C1069G
CY7C1069GE
I/O0I/O7
WE CE2
OE CE1
I/O0I/O7
ERR
WE CE2
OE CE1
Document Number: 001-81539 Rev. *J
Page 2 of 20




 CY7C1069GE
CY7C1069G
CY7C1069GE
Contents
Pin Configurations ........................................................... 4
Product Portfolio .............................................................. 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
AC Switching Characteristics ....................................... 10
Switching Waveforms .................................................... 11
Truth Table – CY7C1069G/CY7C1069GE ...................... 14
ERR Output – CY7C1069GE .......................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC®Solutions ....................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Document Number: 001-81539 Rev. *J
Page 3 of 20






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