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F-RAM Memory. FM22L16 Datasheet

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F-RAM Memory. FM22L16 Datasheet







FM22L16 Memory. Datasheet pdf. Equivalent




FM22L16 Memory. Datasheet pdf. Equivalent





Part

FM22L16

Description

4-Mbit (256K x 16) F-RAM Memory

Manufacture

Cypress Semiconductor

Datasheet
Download FM22L16 Datasheet


Cypress Semiconductor FM22L16

FM22L16; FM22L16 4-Mbit (256K × 16) F-RAM Memory 4-Mbit (256K × 16) F-RAM Memory Feat ures ■ 4-Mbit ferroelectric random ac cess memory (F-RAM) logically organized as 256K × 16 ❐ Configurable as 512K × 8 using UB and LB ❐ High-enduranc e 100 trillion (1014) read/writes ❐ 1 51-year data retention (see the Data Re tention and Endurance table) ❐ NoDela y™ writes ❐ Page mode operation .


Cypress Semiconductor FM22L16

to 25-ns cycle time ❐ Advanced high-re liability ferroelectric process ■ SRA M compatible ❐ Industry-standard 256K × 16 SRAM pinout ❐ 55-ns access tim e, 110-ns cycle time ■ Advanced featu res ❐ Software-programmable block wri te-protect ■ Superior to battery-back ed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True su rface mount solution, no rework steps ❐.


Cypress Semiconductor FM22L16

Superior for moisture, shock, and vibra tion ■ Low power consumption ❐ Acti ve current 8 mA (typ) ❐ Standby curre nt 90 A (typ) ❐ Sleep mode current 5 A (max) ■ Low-voltage operation : VDD = 2.7 V to 3.6 V .



Part

FM22L16

Description

4-Mbit (256K x 16) F-RAM Memory

Manufacture

Cypress Semiconductor

Datasheet
Download FM22L16 Datasheet




 FM22L16
FM22L16
4-Mbit (256K × 16) F-RAM
4-Mbit (256K × 16) F-RAM
Features
4-Mbit ferroelectric random access memory (F-RAM) logically
organized as 256K × 16
Configurable as 512K × 8 using UB and LB
High-endurance 100 trillion (1014) read/writes
151-year data retention (see Data Retention and Endurance
on page 10)
NoDelay™ writes
Page mode operation to 25 ns cycle time
Advanced high-reliability ferroelectric process
SRAM compatible
Industry-standard 256K × 16 SRAM pinout
55-ns access time, 110-ns cycle time
Advanced features
Software-programmable block write-protect
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Low power consumption
Active current 8 mA (typ)
Standby current 90 A (typ)
Sleep mode current 5 A (max)
Low-voltage operation: VDD = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
44-pin thin small outline package (TSOP) Type II
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM22L16 is a 256K × 16 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM22L16 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by CE or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric memory
process. These features make the FM22L16 ideal for nonvolatile
memory applications requiring frequent or rapid writes.
The FM22L16 includes a low voltage monitor that blocks access
to the memory array when VDD drops below VDD min. The
memory is protected against an inadvertent access and data
corruption under this condition. The device also features
software-controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be individually
write protected.
The device is available in a 400-mil, 44-pin TSOP-II surface
mount package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
32 K x 16 block 32 K x 16 block
A17-0
CE
WE
UB, LB
OE
ZZ
A17-2
A 1-0
Control
Logic
32 K x 16 block 32 K x 16 block
32 K x 16 block 32 K x 16 block
32 K x 16 block 32 K x 16 block
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86188 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 21, 2018





 FM22L16
FM22L16
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
Sleep Mode ................................................................. 4
Software Write Protect ................................................ 5
Software Write-Protect Timing .................................... 7
SRAM Drop-In Replacement ....................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 12
Power Cycle and Sleep Mode Timing ........................... 16
Functional Truth Table ................................................... 17
Byte Select Truth Table .................................................. 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-86188 Rev. *G
Page 2 of 22





 FM22L16
FM22L16
Pinout
Figure 1. 44-pin TSOP II pinout
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 44-pin TSOP II 36
10 (× 16) 35
11
12 Top View
13 (not to scale)
34
33
32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
ZZ
A8
A9
A10
A11
A12
Pin Definitions
Pin Name I/O Type
Description
A17–A0
DQ15–DQ0
WE
Input
Input/Output
Input
Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM22L16 to write
the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for
page mode write cycles.
CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the FM22L16 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB
Input
Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
LB
Input
Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
ZZ Input Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ must be HIGH for a normal read/write operation. If unused, tie ZZ pin to VDD.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
Document Number: 001-86188 Rev. *G
Page 3 of 22



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