DatasheetsPDF.com

F-RAM Memory. FM22LD16 Datasheet

DatasheetsPDF.com

F-RAM Memory. FM22LD16 Datasheet






FM22LD16 Memory. Datasheet pdf. Equivalent




FM22LD16 Memory. Datasheet pdf. Equivalent





Part

FM22LD16

Description

4-Mbit (256K x 16) F-RAM Memory



Feature


FM22LD16 4-Mbit (256K × 16) F-RAM Memor y 4-Mbit (256K × 16) F-RAM Memory Fea tures ■ 4-Mbit ferroelectric random a ccess memory (F-RAM) logically organize d as 256K × 16 ❐ Configurable as 512 K × 8 using UB and LB ❐ High-enduran ce 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data R etention and Endurance table) ❐ NoDel ay™ writes ❐ Page mode operation.
Manufacture

Cypress Semiconductor

Datasheet
Download FM22LD16 Datasheet


Cypress Semiconductor FM22LD16

FM22LD16; to 25-ns cycle time ❐ Advanced high-r eliability ferroelectric process ■ SR AM compatible ❐ Industry-standard 256 K × 16 SRAM pinout ❐ 55-ns access ti me, 110-ns cycle time ■ Advanced feat ures ❐ Software-programmable block wr ite-protect ■ Superior to battery-bac ked SRAM modules ❐ No battery concern s ❐ Monolithic reliability ❐ True s urface mount solution, no rework steps .


Cypress Semiconductor FM22LD16

❐ Superior for moisture, shock, and vi bration ■ Low power consumption ❐ A ctive current 8 mA (typ) ❐ Standby cu rrent 90 A (typ) ■ Low-voltage ope ration: VDD = 2.7 V to 3.6 V ■ Indust rial temperature: –40 .


Cypress Semiconductor FM22LD16

.

Part

FM22LD16

Description

4-Mbit (256K x 16) F-RAM Memory



Feature


FM22LD16 4-Mbit (256K × 16) F-RAM Memor y 4-Mbit (256K × 16) F-RAM Memory Fea tures ■ 4-Mbit ferroelectric random a ccess memory (F-RAM) logically organize d as 256K × 16 ❐ Configurable as 512 K × 8 using UB and LB ❐ High-enduran ce 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data R etention and Endurance table) ❐ NoDel ay™ writes ❐ Page mode operation.
Manufacture

Cypress Semiconductor

Datasheet
Download FM22LD16 Datasheet




 FM22LD16
FM22LD16
4-Mbit (256K × 16) F-RAM
4-Mbit (256K × 16) F-RAM
Features
4-Mbit ferroelectric random access memory (F-RAM) logically
organized as 256K × 16
Configurable as 512K × 8 using UB and LB
High-endurance 100 trillion (1014) read/writes
151-year data retention (see Data Retention and Endurance
on page 10)
NoDelay™ writes
Page mode operation to 25 ns cycle time
Advanced high-reliability ferroelectric process
SRAM compatible
Industry-standard 256K × 16 SRAM pinout
55 ns access time, 110 ns cycle time
Advanced features
Software-programmable block write-protect
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Low power consumption
Active current 8 mA (typ)
Standby current 90 A (typ)
Low-voltage operation: VDD = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
48-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
Functional Description
The FM22LD16 is a 256K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM22LD16 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by CE or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric memory
process. These features make the FM22LD16 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The FM22LD16 includes a low voltage monitor that blocks
access to the memory array when VDD drops below VDD min.
The memory is protected against an inadvertent access and data
corruption under this condition. The device also features
software-controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be individually
write protected.
The device is available in a 48-ball FBGA package. Device
specifications are guaranteed over the industrial temperature
range –40 °C to +85 °C.
For a complete list of related documentation, click here.
32 K x 16 block 32 K x 16 block
A17-0
CE
WE
UB, LB
OE
A17-2
A1-0
Control
Logic
32 K x 16 block 32 K x 16 block
32 K x 16 block 32 K x 16 block
32 K x 16 block 32 K x 16 block
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86190 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 21, 2018




 FM22LD16
FM22LD16
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
Software Write Protect ................................................ 4
Software Write-Protect Timing .................................... 7
SRAM Drop-In Replacement ....................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 12
Power Cycle and Sleep Mode Timing ........................... 16
Functional Truth Table ................................................... 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-86190 Rev. *G
Page 2 of 22




 FM22LD16
Pinout
Figure 1. 48-ball FBGA pinout
(× 16)
Top View
(not to scale)
12
34
56
LB OE A0 A1 A2 NC
DQ8 UB A3 A4 CE DQ0
DQ9 DQ10 A5
A6 DQ1 DQ2
VSS DQ11 A17 A7 DQ3 VDD
VDD DQ12 NC A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 NC A12 A13 WE DQ7
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
FM22LD16
Pin Definitions
Pin Name I/O Type
Description
A17–A0
DQ15–DQ0
WE
Input
Input/Output
Input
Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM22LD16 to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the FM22LD16 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB
Input
Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
LB
Input
Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
Document Number: 001-86190 Rev. *G
Page 3 of 22






Recommended third-party FM22LD16 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)