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I2C F-RAM. FM24C04B Datasheet

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I2C F-RAM. FM24C04B Datasheet







FM24C04B F-RAM. Datasheet pdf. Equivalent




FM24C04B F-RAM. Datasheet pdf. Equivalent





Part

FM24C04B

Description

4-Kbit (512 x 8) Serial (I2C) F-RAM

Manufacture

Cypress Semiconductor

Datasheet
Download FM24C04B Datasheet


Cypress Semiconductor FM24C04B

FM24C04B; FM24C04B 4-Kbit (512 × 8) Serial (I2C) F-RAM 4-Kbit (512 × 8) Serial (I2C) F -RAM Features ■ 4-Kbit ferroelectric random access memory (F-RAM) logically organized as 512 × 8 ❐ High-enduranc e 100 trillion (1014) read/writes ❐ 1 51-year data retention (See Data Retent ion and Endurance on page 10) ❐ NoDel ay™ writes ❐ Advanced high-reliabil ity ferroelectric process ■ Fast .


Cypress Semiconductor FM24C04B

2-wire Serial interface (I2C) ❐ Up to 1-MHz frequency ❐ Direct hardware rep lacement for serial (I2C) EEPROM ❐ Su pports legacy timings for 100 kHz and 4 00 kHz ■ Low power consumption ❐ 10 0 A active current at 100 kHz ❐ 4 A (typ) standby current ■ Voltage operation: VDD = 4.5 V to 5.5 V ■ AEC -Q100 grade 3 qualified ■ Industrial temperature: –40 C to +85 C ■ 8-pin sm.


Cypress Semiconductor FM24C04B

all outline integrated circuit (SOIC) pa ckage ■ Restriction of hazardous subs tances (RoHS) compliant Functional Des cription The FM24C04B is a 4-Kbit nonvo latile memory employing an advanced fer roelectric process. A ferroelectric ran dom access memory or F-RAM is nonvolati le and performs reads and writes simila r to a RAM. It provides reliable data r etention for 151 yea.



Part

FM24C04B

Description

4-Kbit (512 x 8) Serial (I2C) F-RAM

Manufacture

Cypress Semiconductor

Datasheet
Download FM24C04B Datasheet




 FM24C04B
FM24C04B
4-Kbit (512 × 8) Serial (I2C) F-RAM
4-Kbit (512 × 8) Serial (I2C) F-RAM
Features
4-Kbit ferroelectric random access memory (F-RAM) logically
organized as 512 × 8
High-endurance 100 trillion (1014) read/writes
151-year data retention (See Data Retention and Endurance
on page 10)
NoDelay™ writes
Advanced high-reliability ferroelectric process
Fast 2-wire Serial interface (I2C)
Up to 1-MHz frequency
Direct hardware replacement for serial (I2C) EEPROM
Supports legacy timings for 100 kHz and 400 kHz
Low power consumption
100 A active current at 100 kHz
4 A (typ) standby current
Voltage operation: VDD = 4.5 V to 5.5 V
AEC-Q100 grade 3 qualified
Industrial temperature: –40 C to +85 C
8-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM24C04B is a 4-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24C04B performs write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24C04B
is capable of supporting 1014 read/write cycles, or 100 million
times more write cycles than EEPROM.
These capabilities make the FM24C04B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24C04B provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The device
specifications are AEC-Q100 qualified and guaranteed over an
industrial temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
Counter
Address
Latch
9
SDA
SCL
WP
A2-A1
Serial to Parallel
Converter
Control Logic
8
512 x 8
F-RAM Array
8
Data Latch
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84446 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 5, 2018





 FM24C04B
FM24C04B
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
I2C Interface ...................................................................... 4
STOP Condition (P) ..................................................... 4
START Condition (S) ................................................... 4
Data/Address Transfer ................................................ 5
Acknowledge/No-acknowledge ................................... 5
Slave Device Address ................................................. 6
Addressing Overview (Word Address) ........................ 6
Data Transfer .............................................................. 6
Memory Operation ............................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Endurance ......................................................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
Power Cycle Timing ....................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-84446 Rev. *M
Page 2 of 18





 FM24C04B
FM24C04B
Pinout
Figure 1. 8-pin SOIC pinout
NC 1
8
A1 2 Top View 7
not to scale
A2 3
6
VSS 4
5
VDD
WP
SCL
SDA
Pin Definitions
Pin Name
A2–A1
SDA
SCL
WP
VSS
VDD
I/O Type
Description
Input
Device Select Address 2–1. These pins are used to select one of up to 4 devices of the same type
on the same I2C bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
Input
Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
Input
Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
Document Number: 001-84446 Rev. *M
Page 3 of 18



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